AM79C971VCW datasheet(77/265 Pages) AMD

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Am79C971

pa th, RXD (3:0 ), from the exter n al PHY to th e

Am79C971 controller and is synchronous to the rising

edge of RX_CLK.

The receive process starts when RX_DV is asserted.

RX_DV will remain asserted until the end of the receive

frame. The Am79C971 controller requires CRS (Car-

rier Sense) to toggle in between frames in order to re-

ceive them properly. Errors in the currently received

frame are signaled across the MII by the RX_ER pin.

RX_ER can be used to signal special conditions out of

band when RX_DV is not asserted. Two defined out-of-

band conditions for this are the 100BASE-TX signaling

of bad Start of Frame Delimiter and the 100BASE-T4

indication of illegal code group before the receiver has

synched to the incoming data. The Am79C971 control-

ler will not respond to these conditions. All out of band

conditions are currently treated as NULL events. Cer-

tain in band non-IEEE 802.3u-compliant flow control

sequences may cause erratic behavior for the

Am79C971 controller. Consult the switch/bridge/router/

hub manual to disable the in-band flow control se-

quences if they are being used.

MII Network Status Interface

The MII also provides signals that are consistent and

necessary for IEEE 802.3 and IEEE 802.3u operation.

These signals are CRS (Carrier Sense) and COL (Col-

lision Sense). Carrier Sense is used to detect non-idle

activity on the network. Collision Sense is used to indi-

cate that simultaneous transmission has occurred in a

half-duplex network.

MII Management Interface

The MII provides a two-wire management interface so

that the Am79C971 controller can control and receive

status from external PHY devices.

The Am79C971 controller can support up to 31 exter-

nal PHYs attached to the MII Management Interface

with software support and only one such device without

software support.

The Network Port Manager copies the PHYAD after the

Am79C971 controller reads the EEPROM and uses it

to communicate with the external PHY. The PHY ad-

dress must be programmed into the EEPROM prior to

starting the Am79C971 controller. This is necessary so

that the internal management controller can work au-

tonomously from the software driver and can always

know where to ac cess the exter n al PHY. T h e

Am79C971 controller is unique by offering direct hard-

ware support of the external PHY device without soft-

ware support. The internal PHY is addressed at the last

available MII address of 1Fh. To access the 31 external

PHYs, the software driver must have knowledge of the

external PHY’s address when multiple PHYs are

present before attempting to address it.

The MII Management Interface uses the MII Control,

Address, and Data registers (BCR32, 33, 34) to control

and communicate to the exter nal an d inter nal

10BASE-T only PHYs. Am79C971 generates MII man-

agement frames to the external PHY through the MDIO

pin synchronous to the rising edge of the Management

Data Clock (MDC) based on a combination of writes

and reads to these registers. To prevent problems on

the exposed interface, MII management frames will not

be generated when the internal PHY is the target. The

MII only supports internal and external 10BASE-T or

100BASE-T as possible network connections. The in-

ternal AUI and GPSI are not considered part of the MII

and cannot be selected through the MII.

Figure 38.

Media Independent Interface

RXD(3:0)

RX_DV

RX_ER

RX_CLK

TXD(3:0)

TX_EN

TX_ER

TX_CLK

Am79C971

MDIO

MDC

COL

CRS

Receive Signals

Transmit Signals

Management Port Signals

Network Status Signals

20550D-41

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