AM79C971VCW datasheet(37/265 Pages) AMD

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Am79C971

Figure 11 shows the Am79C971controller bus acquisi-

tion. REQ is asserted and the arbiter returns GNT while

an othe r bu s m a s t e r i s tran sfer r i ng dat a. T h e

Am79C971 controller waits until the bus is idle (FRAME

and IRDY deasserted) before it starts driving AD[31:0]

and C/BE[3:0] on clock 5. FRAME is asserted at clock

5 indicating a valid address and command on AD[31:0]

and C/BE[3:0]. The Am79C971 controller does not use

address stepping which is reflected by ADSTEP (bit 7)

in the PCI Command register being hardwired to 0.

Figure 11.

Bus Acquisition

In burst mode, the deassertion of REQ depends on the

setting of EXTREQ (BCR18, bit 8). If EXTREQ is

cleared to 0, REQ is deasserted at the same time as

FRAME is asserted. (The Am79C971 controller never

performs more than one burst transaction within a sin-

gle bus mastership period.) If EXTREQ is set to 1, the

Am79C971 controller does not deassert REQ until it

starts the last data phase of the transaction.

Once asserted, REQ remains active until GNT has be-

come active and independent of subsequent setting of

STOP (CSR0, bit 2) or SPND (CSR5, bit 0). The asser-

tion of H_RESET or S_RESET, however, will cause

REQ to go inactive immediately.

Bus Master DMA Transfers

There are four primary types of DMA transfers. The

Am79C971 controller uses non-burst as well as burst

cycles for read and write access to the main memory.

Basic Non-Burst Read Transfer

By default, the Am79C971 controller uses non-burst

cycles in all bus master read operations. All Am79C971

controller non-burst read accesses are of the PCI

command type Memory Read (type 6). Note that during

a non-burst read operation, all byte lanes will always be

active. The Am79C971 controller will internally discard

unneeded bytes.

The Am79C971 controller typically performs more than

one non-burst read transactions within a single bus

mastership period. FRAME is dropped between con-

secutive non-burst read cycles. REQ however stays as-

serted until FRAME is asserted for the last transaction.

The Am79C971 controller supports zero wait state

read cycles. It asserts IRDY immediately after the ad-

dress phase and at the same time starts sampling

DEVSEL. Figure 12 shows two non-burst read transac-

tions. The first transaction has zero wait states. In the

second transaction, the target extends the cycle by as-

serting TRDY one clock later.

Basic Burst Read Transfer

The Am79C971 controller supports burst mode for all

bus master read operations. The burst mode must be

enabled by setting BREADE (BCR18, bit 6). To allow

burst transfers in descriptor read operations, the

Am79C971 controller must also be programmed to use

SWSTYLE 3 (BCR20, bits 7-0). All burst read accesses

to the initialization block and descriptor ring are of the

PCI command type Memory Read (type 6). Burst read

accesses to the transmit buffer typically are longer than

two data phases. When MEMCMD (BCR18, bit 9) is

cleared to 0, all burst read accesses to the transmit

buffer are of the PCI command type Memory Read Line

(type 14). When MEMCMD (BCR18, bit 9) is set to1, all

burst read accesses to the transmit buffer are of the

PCI command type Memory Read Multiple (type 12).

AD[1:0] will both be 0 during the address phase indicat-

ing a linear burst order. Note that during a burst read

operation, all byte lanes will always be active. The

Am79C971 controller will internally discard unneeded

bytes.

The Am79C971 controller will always perform only a

single burst read transaction per bus mastership pe-

riod, where transaction is defined as one address

ph as e an d o n e or mul t i p l e da ta p h a s es. T h e

Am79C971 controller supports zero wait state read cy-

cles. It asserts IRDY immediately after the address

phase and at the same time starts sampling DEVSEL.

FRAME is deasserted when the next to last data phase

is completed. Figure 13 shows a typical burst read ac-

cess. The Am79C971 controller arbitrates for the bus,

is granted access, reads three 32-bit words (DWord)

from the system memory, and then releases the bus. In

the example, the memory system extends the data

phase of the each access by one wait state. The exam-

ple assumes that EXTREQ (BCR18, bit 8) is cleared to

0, therefore, REQ is deasserted in the same cycle as

FRAME is asserted.

FRAME

CLK

IRDY

C/BE

REQ

GNT

2345

CMD

ADDR

20550D-14

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