AM79C971VCW datasheet(54/265 Pages) AMD

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Am79C971

Note that this form of restart will not perform the same

in the Am79C971 controller as in the C-LANCE device.

In particular, upon restart, the Am79C971 controller re-

loads the transmit and receive descriptor pointers with

their respective base addresses. This means that the

software must clear the descriptor OWN bits and reset

its descriptor ring pointers before restar ting the

Am79C971 controller. The reload of descriptor base

addresses is performed in the C-LANCE device only

after initialization, so that a restart of the C-LANCE

without initialization leaves the C-LANCE pointing at

the same descriptor locations as before the restart.

Suspend

The Am79C971 controller offers two suspend modes

that allows easy updating of the CSR registers without

going through a full re-initialization of the device. The

suspend modes also allow stopping the device with or-

derly termination of all network activity.

The host requests the Am79C971 controller to enter

the suspend mode by setting SPND (CSR5, bit 0) to 1.

The host must poll SPND until it reads back 1 to deter-

mine that the Am79C971 controller has entered the

suspend mode. When the host sets SPND to 1, the pro-

cedure taken by the Am79C971 controller to enter the

suspend mode depends on the setting of the fast sus-

pend enable bit (FASTSPND, CSR7, bit 15).

When a fast suspend is requested (FASTSPND is set

to 1), the Am79C971 controller performs a quick entry

into the suspend mode. At the time the SPND bit is set,

the Am79C971 controller will continue the DMA pro-

cess of any transmit and/or receive packets that have

already begun DMA activity until the network activity

has been completed. In addition, any transmit packet

that had started transmission will be fully transmitted

and any receive packet that had begun reception will be

fully received. However, no additional packets will be

transmitted or received and no additional transmit or re-

ceive DMA activity will begin after network activity has

ceased. Hence, the Am79C971 controller may enter

the suspend mode with transmit and/or receive packets

still in the FIFOs or external SRAM. This offers a worst

case suspend time of a maximum length packet over

the possibility of completely emptying the external

SRAM. Care must be exercised in this mode, because

the entire memory subsystem of the Am79C971 con-

troller is suspended. Any changes to either the descrip-

tor r ings or the exter nal SRAM can cause the

Am79C971 controller to start up in an unknown condi-

tion and could cause data corruption.

When FASTSPNDE is 0 and the SPND bit is set, the

Am79C971 controller may take longer before entering

the suspend mode. At the time the SPND bit is set, the

Am79C971 controller will complete the DMA process of

a transmit packet if it had already begun and the

Am79C971 controller will completely receive a receive

packet if it had already begun. The Am79C971 control-

ler will not receive any new packets after the comple-

tion of the current reception. Additionally, all transmit

packets stored in the transmit FIFOs and the transmit

buffer area in the external SRAM (if one is present) will

be transmitted, and all receive packets stored in the re-

ceive FIFOs and the receive buffer area in the external

SRAM (if one is present) will be transferred into system

memory. Since the FIFO and external SRAM contents

are flushed, it may take much longer before the

Am79C971 controller enters the suspend mode. The

amount of time that it takes depends on many factors

including the size of the external SRAM, bus latency,

and network traffic level.

Upon completion of the described operations, the

Am79C971 controller sets the read-version of SPND to

1 and enters the suspend mode. In suspend mode, all

of the CSR and BCR registers are accessible. As long

as the Am79C971 controller is not reset while in sus-

pend mode (by H_RESET, S_RESET, or by setting the

STOP bit), no re-initialization of the device is required

after the device comes out of suspend mode. When

SPND is set to 0, the Am79C971 controller will leave

the suspend mode and will continue at the transmit and

receive descriptor ring locations, where it had been

when it entered the suspend mode.

See the section on Magic Packet™ technology for de-

tails on how that affects suspension of the Am79C971

controller.

Buffer Management

Buffer management is accomplished through message

descriptor entries organized as ring structures in mem-

ory. There are two descriptor rings, one for transmit and

one for receive. Each descriptor describes a single

buffer. A frame may occupy one or more buffers. If mul-

tiple buffers are used, this is referred to as buffer chain-

ing.

Descriptor Rings

Each descriptor ring must occupy a contiguous area of

memory. During initialization, the user-defined base

address for the transmit and receive descriptor rings,

as well as the number of entries contained in the de-

scriptor rings are set up. The programming of the soft-

ware style (SWSTYLE, BCR20, bits 7-0) affects the

way the descriptor rings and their entries are arranged.

When SWSTYLE is at its default value of 0, the de-

scriptor rings are backwards compatible with the

Am79C90 C-LANCE and the Am79C96x PCnet-ISA

family. The descriptor ring base addresses must be

aligned to an 8-byte boundary and a maximum of 128

ring entries is allowed when the ring length is set

through the TLEN and RLEN fields of the initialization

block. Each ring entry contains a subset of the three

32-bit transmit or receive message descriptors (TMD,

RMD) that are organized as four 16-bit structures

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