AM79C971VCW datasheet(83/265 Pages) AMD

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Am79C971

address decoding systems, the SFBD signal will go

HIGH at each new byte boundary within the packet,

subsequent to the SFD. This eliminates the need for ex-

ternally supplying byte framing logic.

The EAR pin function is the same and should be driven

LOW by the external address comparison logic to reject

a frame.

External Address Detection Interface: Receive

Frame Tagging

The Am79C971 controller supports receive frame tag-

ging in both internal PHY mode or in the MII mode. The

method remains constant, but the chip interface pins

will change between the MII and the internal PHY

modes. The receive frame tagging implementation will

be a two- and three-wire chip interface, respectively,

added to the existing EADI.

The Am79C971 controller supports up to 15 bits of re-

ceive frame tagging per frame in the receive frame sta-

tus (RFRTAG). The RFRTAG bits are in the receive

frame status field in RMD2 (bits 30-16) in 32-bit soft-

ware mode. The receive frame tagging is not supported

in the 16-bit software mode. The RFRTAG field are all

zeros when either the EADISEL (BCR2, bit3) or the

RXFRTAG (CSR7, bit 14) are set to 0. When EADISEL

(BCR2, bit 3) and RXFRTAG (CSR7, bit 14) are set to

1, then the RFRTAG reflects the tag word shifted in dur-

ing that receive frame.

In the MII mode, the two-wire interface will use the

MIIRXFRTGD and MIIRXFRTGE pins from the EADI

interface. These pins will provide the data input and

data input enable for the receive frame tagging, respec-

tively. These pins are normally not used during the MII

operation.

In the internal PHY mode, the three-wire interface will

use the RXFRTGD, SRDCLK, and the RXFRTGE pins

from the EADI and MII. These pins will provide the data

input, data input clock, and the data input for the re-

ceive frame tagging enable, respectively.

The receive frame tag register is a shift register that

shifts data in MSB first, so that less than the 15 bits al-

located may be utilized by the user. The upper bits not

utilized will return zeros. The receive frame tag register

is set to 0 in between reception of frames. After receiv-

ing SFBD indication on the EADI, the user can start

shifting data into the receive tag register until one net-

work clock period before the Am79C971 controller re-

ceives the end of the current receive frame.

In the MII mode, the user must see the RX_CLK to

drive the synchronous receive frame tag data interface.

After receiving the SFBD indication, sampled by the ris-

ing edge of the RX_CLK, the user will drive the data

input and the data input enable synchronous with the

rising edge of the RX_CLK. The user has until one net-

work clock period before the deassertion of the RX_DV

to input the data into the receive frame tag register. At

the deassertion of the RX_DV, the receive frame tag

terface. If the user is still driving the data input enable

pin, erroneous or corrupted data may reside in the re-

ceive frame tag register. See Figure 40.

In the internal PHY mode, the user must use the recov-

ered receive data clock driven on the SRDCLK pin to

drive the synchronous receive frame tag data interface.

After receiving the SFBD indication, sampled by the ris-

ing edge of the recovered receive data clock, the user

will drive the data input and the data input enable syn-

chronous with the rising edge of the recovered receive

data clock. The user has until one network clock period

before the deassertion of the data from the network to

input the data into the receive frame tag register. At the

completion of received network data, the receive frame

tag register will no longer accept data from the two-wire

interface. If the user is still driving the data input enable

pin, erroneous or corrupted data may reside in the re-

ceive frame tag register. See Figure 41.

Figure 40.

MII Receive Frame Tagging

RX_CLK

RX_DV

MIIRXFRTGE

MIIRXFRTGD

SF/BD

20550D-44

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