AM79C971VCW datasheet(40/265 Pages) AMD

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Am79C971

Figure 15 shows a typical burst write access. The

Am79C971 controller arbitrates for the bus, is granted

access, and writes four 32-bit words (DWords) to the

system memory and then releases the bus. In this ex-

ample, the memory system extends the data phase of

the first access by one wait state. The following three

data phases take one clock cycle each, which is deter-

mined by the timing of TRDY. The example assumes

that EXTREQ (BCR18, bit 8) is set to 1, therefore, REQ

is not deasserted until the next to last data phase is fin-

ished.

Target Initiated Termination

When the Am79C971 controller is a bus master, the cy-

cles it produces on the PCI bus may be terminated by

the target in one of three different ways.

Disconnect With Data Transfer

Figure 16 shows a disconnection in which one last data

transfer occurs after the target asserted STOP. STOP

is asserted on clock 4 to start the termination se-

quence. Data is still transferred during this cycle, since

both IRDY and TRDY are asserted. The Am79C971

controller terminates the current transfer with the deas-

sertion of FRAME on clock 5 and of IRDY one clock

later. It finally releases the bus on clock 7. The

Am79C971 controller will again request the bus after

two clock cycles, if it wants to transfer more data. The

starting address of the new transfer will be the address

of the next non-transferred data.

Figure 15.

Burst Write Transfer (EXTREQ = 1)

FRAME

CLK

IRDY

TRDY

C/BE

EVSEL

REQ

GNT

2345678

ADDR

DATA

0111

PAR

DATA

PAR

DEVSEL is sampled

20550D-18

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