AM79C971VCW datasheet(28/265 Pages) AMD

28 / 265 page

Am79C971

When RST is active, MIIRXFRTGE is an input for

NAND tree testing.

IEEE 1149.1 (1990) Test Access Port

Interface

TCK

Test Clock

Input

TCK is the clock input for the boundary scan test mode

operation. It can operate at a frequency of up to 10

MHz. TCK has an internal pull up resistor.

TDI

Test Data In

Input

TDI is the test data input path to the Am79C971 con-

troller. The pin has an internal pull up resistor.

TDO

Test Data Out

Output

TDO is the test data output path from the Am79C971

controller. The pin is tri-stated when the JTAG port is in-

active.

TMS

Test Mode Select

Input

A serial input bit stream on the TMS pin is used to de-

fine the specific boundary scan test to be executed.

The pin has an internal pull up resistor.

Power Supply Pins

AVDDB

Analog Power (3 Pins)

Power

There are three analog +5 V supply pins that provide

power for the Twisted Pair and AUI drivers. Hence, they

are very noisy. Special attention should be paid to the

printed circuit board layout to avoid excessive noise on

these lines. Refer to Appendix B, Recommendation for

Power and Ground Decoupling, for details.

AVSSB

Analog Ground (1 Pins)

Power

There is one analog ground pin that provides ground

for the Twisted Pair and AUI drivers. Hence, it is very

noisy. Special attention should be paid to the printed

circuit board layout to avoid excessive noise on these

lines. Refer to Appendix B, Recommendation for Power

and Ground Decoupling, for details.

VDD_PLL

PLL Power (1 Pin)

Power

There is one analog PLL +5 V supply pin. Special at-

tention should be paid to the printed circuit board layout

to avoid excessive noise on this line. Refer to Appendix

B, Recommendation for Power and Ground Decou-

pling, for details.

VSS_PLL

PLL Ground (1 Pin)

Power

There is one analog PLL ground pin. Special attention

should be paid to the printed circuit board layout to

avoid excessive noise on this line. Refer to Appendix B,

Recommendation for Power and Ground Decoupling,

for details.

VDDB

I/O Buffer Power (5 Pins)

Power

There are five power supply pins that are used by the

input/output buffer drivers. All VDDB pins must be con-

nected to a +5 V supply.

VSSB

I/O Buffer Ground (13 Pins)

Power

There are thirteen ground pins that are used by the PCI

bus input/output buffer drivers.

VDD_PCI

PCI I/O Buffer Power (5 Pins)

Power

There are five power supply pins that are used by the

PCI input/output buffer drivers. In a system with +5 V

signaling environment, all VDD_PCI pins must be con-

nected to a +5 V supply. In a system with +3.3 V signal-

ing environment, all VDD_PCI pins must be connected

to a +3.3 V supply.

VDD

Digital Power (4 Pins)

Power

There are four power supply pins that are used by the

internal digital circuitry. All VDD pins must be con-

nected to a +5 V supply.

VSS

Digital Ground (6 Pins)

Power

There are six ground pins that are used by the internal

digital circuitry.

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