AM79C971VCW datasheet(94/265 Pages) AMD

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Am79C971

Figure 53.

Typical SRAM Write Operation

SRAM Interface Bandwidth Requirements

When the EBCLK pin is used to drive the Expansion

Bus cycles and external SRAMs are present, the

CLK_FAC (BCR27, bits 2-0) selects the clock factor for

the Expansion Bus Clock (EBCLK). The Expansion

Bus Clock can be divided down by factors of 2 or 4. For

maximum throughput capability to support maximum

wire rates in a full-duplex 100-Mbps network, a 33-MHz

clock should be supplied to the EBCLK input pin and

15-ns SRAM devices must be used. For systems with

lower throughput requirements, a lower clock fre-

quency, along with slower speed SRAM devices, may

be used. In a half-duplex 10-Mbps design, an EBCLK

frequency as low as 2.5 MHz may be used, while still

providing sufficient bandwidth on the SRAM interface

to keep up with maximum wire data rates.

Frequency Demands for Network Operation

The minimum supported clock frequency on the Ex-

pansion Bus for normal network operations is 10 MHz.

The minimum supported clock frequency on the PCI

Bus for normal network operations is 15 MHz. The PCI

clock pin can be stopped or run at any frequency, but

may give underflows and overflows due to reduced

bandwidth. These minimum requirements apply only to

10-Mbps half-duplex operation. Details of the clock fre-

quency and SRAM depth requirements for typical net-

work can be found in the PCnet Fast Buffer Memory

Performance White Paper, PID #20898A.

EEPROM Interface

The Am79C971 controller contains a built-in capability

for reading and writing to an external serial 93C46

EEPROM. This built-in capability consists of an inter-

face for direct connection to a 93C46 compatible

EEPROM, an automatic EEPROM read feature, and a

user-programmable register that allows direct access

to the interface pins.

Automatic EEPROM Read Operation

Shortly after the deassertion of the RST pin, the

Am79C971 controller will read the contents of the

EEPROM that is attached to the interface. Because of

this automatic-read capability of the Am79C971 con-

troller, an EEPROM can be used to program many of

the features of the Am79C971 controller at power-up,

allowing system-dependent configuration information

to be stored in the hardware, instead of inside the

device driver.

If an EEPROM exists on the interface, the Am79C971

controller will read the EEPROM contents at the end of

the H_RESET operation. The EEPROM contents will

be serially shifted into a temporary register and then

sent to various register locations on board the

Am79C971 controller. Access to the Am79C971 con-

figuration space, the Expansion ROM or any I/O

resource is not possible during the EEPROM read op-

eration. The Am79C971 controller will terminate any

access attempt with the assertion of DEVSEL and

STOP while TRDY is not asserted, signaling to the ini-

tiator to disconnect and retry the access at a later time.

A checksum verification is performed on the data that

is read from the EEPROM. If the checksum verification

passes, PVALID (BCR19, bit 15) will be set to 1. If the

checksum verification of the EEPROM data fails,

PVALID will be cleared to 0, and the Am79C971 con-

troller will force all EEPROM-programmable BCR reg-

isters back to their H_RESET default values. However,

the content of the Address PROM locations (offsets

0h - Fh from the I/O or memory mapped I/O base ad-

dress) will not be cleared. The 8-bit checksum for the

entire 64 bytes of the EEPROM should be FFh.

If no EEPROM is present at the time of the automatic

read operation, the Am79C971 controller will recognize

this condition and will abort the automatic read opera-

tion and clear both the PREAD and PVALID bits in

BCR19. All EEPROM-programmable BCR registers

will be assigned their default values after H_RESET.

The content of the Address PROM locations (offsets

0h - Fh from the I/O or memory mapped I/O base ad-

dress) will be undefined.

AS_EBOE

EBUA_EBA[7:0]

EBCLK

EBD[15:0]

7:0

7:0 7:0 7:0 7:0 7:0 7:0 7:0

7:0 7:0 7:0

7:0 7:0

ERAMCS

EBWE

15:8

20550D-56

Note:

EBD[15:0] = EBDA[15:8]+EBD[7:0]

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