AM79C971VCW datasheet(49/265 Pages) AMD

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Am79C971

If buffer chaining is used, accesses to the descriptors

of all intermediate buffers consist of only one data

transfer to return ownership of the buffer to the system.

When SWSTYLE (BCR20, bits 7-0) is cleared to 0 (i.e.,

the descriptor entries are organized as 16-bit software

structures), the descriptor access will write a single

byte. When SWSTYLE (BCR20, bits 7-0) is set to 2 or

3 (i.e., the descriptor entries are organized as 32-bit

software structures), the descriptor access will write a

single word. On all single buffer transmit or receive de-

scriptors, as well as on the last buffer in chain, writes to

the descriptor consist of two data transfers.

The first data transfer writes a DWord containing status

information. The second data transfer writes a byte

(SWSTYLE cleared to 0), or otherwise a word contain-

ing additional status and the ownership bit (i.e.,

MD1[31]).

The settings of SWSTYLE (BCR20, bits 7-0) and

BWRITE (BCR18, bit 5) affect the way the Am79C971

controller performs descriptor write operations.

When SWSTYLE is set to 0 or 2, all descriptor write op-

erations are performed in non-burst mode. The setting

of BWRITE has no effect in this configuration.

When SWSTYLE is set to 3, the descriptor entries are

ordered to allow burst transfers. The Am79C971 con-

troller will perform all descriptor write operations in

burst mode, if BWRITE is set to 1. See Table 5 for the

descriptor write sequence.

A write transaction to the descriptor ring entries is the

only case where the Am79C971 controller inserts a

wait state when being the bus master. Every data

phase in non-burst and burst mode is extended by one

clock cycle, during which IRDY is deasserted.

Note that Figure 26 assumes that the Am79C971 con-

troller is programmed to use 32-bit software structures

(SWSTYLE = 2 or 3). The byte enable signals for the

second data transfer would be 0111b, if the device was

programmed to use 16-bit software structures (SW-

STYLE = 0).

Figure 26.

Descriptor Ring Read In Burst Mode

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

REQ

GNT

234567

MD1

0000

0110

PAR

DATA

PAR

DEVSEL is sampled

20550D-29

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