AM79C971VCW datasheet(30/265 Pages) AMD

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Am79C971

DETAILED FUNCTIONS

Slave Bus Interface Unit

The slave bus interface unit (BIU) controls all accesses

to the PCI configuration space, the Control and Status

Registers (CSR), the Bus Configuration Registers

(BCR), the Address PROM (APROM) locations, and

the Expansion ROM. Table 2 shows the response of

the Am79C971 controller to each of the PCI commands

in slave mode.

Table 2.

Slave Commands

Slave Configuration Transfers

The host can access the Am79C971 PCI configuration

space with a configuration read or write command. The

Am79C971 controller will assert DEVSEL during the

address phase when IDSEL is asserted, AD[1:0] are

both 0, and the access is a configuration cycle. AD[7:2]

select the DWord location in the configuration space.

The Am79C971 controller ignores AD[10:8], because it

is a single function device. AD[31:11] are don’t care.

The active bytes within a DWord are determined by the

byte enable signals. Eight-bit, 16-bit, and 32-bit trans-

fers are supported. DEVSEL is asserted two clock cy-

cles a f t e r t h e h o st ha s a sser t ed FR AM E . A ll

co nf ig ura t io n cycle s are of f i xe d le n g t h . The

Am79C971 controller will assert TRDY on the third

clock of the data phase.

The Am79C971 controller does not support burst trans-

fers for access to configuration space. When the host

keeps FRAME asserted for a second data phase, the

Am79C971 controller will disconnect the transfer.

When the host tries to access the PCI configuration

space while the automatic read of the EEPROM after

H_RESET (see section on RESET) is on-going, the

Am79C971 controller will terminate the access on the

PCI bus with a disconnect/retry response.

The Am79C971 controller supports fast back-to-back

transactions to different targets. This is indicated by the

Fast Back-To-Back Capable bit (PCI Status register, bit

7), which is hardwired to 1. The Am79C971 controller

is capable of detecting a configuration cycle even when

its address phase immediately follows the data phase

of a transaction to a different target without any idle

state in-between. There will be no contention on the

DEVSEL , TR DY, and STOP sign als, since th e

Am79C971 controller asserts DEVSEL on the second

clock after FRAME is asserted (medium timing).

Slave I/O Transfers

After the Am79C971 controller is configured as an I/O

device by setting IOEN (for regular I/O mode) or

MEMEN (for memory mapped I/O mode) in the PCI

Command register, it starts monitoring the PCI bus for

access to its CSR, BCR, or APROM locations. If con-

figured for regular I/O mode, the Am79C971 controller

will look for an address that falls within its 32 bytes of I/

O address space (starting from the I/O base address).

The Am79C971 controller asserts DEVSEL if it detects

an address match and the access is an I/O cycle. If

con figured for memor y mapped I/O m ode, th e

Am79C971 controller will look for an address that falls

within its 32 bytes of memory address space (starting

from the memory mapped I/O base address). The

Am79C971 controller asserts DEVSEL if it detects an

address match and the access is a memory cycle.

DEVSEL is asserted two clock cycles after the host has

asserted FRAME. See Figure 1 and Figure 2.

C[3:0]

Command

Use

0000

Interrupt

Acknowledge

Not used

0001

Special Cycle

Not used

0010

I/O Read

Read of CSR, BCR, APROM,

and Reset registers

0011

I/O Write

Write to CSR, BCR, and

APROM

0100

Reserved

0101

Reserved

0110

Memory Read

Memory mapped I/O read of

CSR, BCR, APROM, and

Reset registers

Read of the Expansion Bus

0111

Memory Write

Memory mapped I/O write of

CSR, BCR, and APROM

1000

Reserved

1001

Reserved

1010

Configuration

Read

Read of the Configuration

Space

1011

Configuration

Write

Write to the Configuration

Space

1100

Memory Read

Multiple

Aliased to Memory Read

1101

Dual Address

Cycle

Not used

1110

Memory Read

Line

Aliased to Memory Read

1111

Memory Write

Invalidate

Aliased to Memory Write

AD31

AD11

AD10

AD8

AD7

AD2

AD1

AD0

Don’t care

DWord

index

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