AM79C971VCW datasheet(55/265 Pages) AMD

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Am79C971

(SSIZE32 (BCR20, bit 8) is set to 0). Note that even

though the Am79C971 controller treats the descriptor

entries as 16-bit structures, it will always perform 32-bit

bus transfers to access the descriptor entries. The

value of CSR2, bits 15-8, is used as the upper 8-bits for

all memory addresses during bus master transfers.

When SWSTYLE is set to 2 or 3, the descriptor ring

base addresses must be aligned to a 16-byte bound-

ary, and a maximum of 512 ring entries is allowed when

the ring length is set through the TLEN and RLEN fields

of the initialization block. Each ring entry is organized

as three 32-bit message descriptors (SSIZE32

(BCR20, bit 8) is set to 1). The fourth DWord is re-

served. When SWSTYLE is set to 3, the order of the

message descriptors is optimized to allow read and

write access in burst mode.

For any software style, the ring lengths can be set be-

yond this range (up to 65535) by writing the transmit

and receive ring length registers (CSR76, CSR78) di-

rectly.

Each ring entry contains the following information:

s The address of the actual message data buffer in

user or host memory

s The length of the message buffer

s Status information indicating the condition of the

buffer

To permit the queuing and de-queuing of message

buffers, ownership of each buffer is allocated to either

the Am79C971 controller or the host. The OWN bit

within the descriptor status information, either TMD or

RMD, is used for this purpose.

When OWN is set to 1, it signifies that the Am79C971

controller currently has ownership of this ring descrip-

tor and its associated buffer. Only the owner is permit-

ted to relinquish ownership or to write to any field in the

descriptor entry. A device that is not the current owner

of a descriptor entry cannot assume ownership or

change any field in the entry. A device may, however,

read from a descriptor that it does not currently own.

Software should always read descriptor entries in se-

quential order. When software finds that the current de-

scriptor is owned by the Am79C971 controller, then the

software must not read ahead to the next descriptor.

The software should wait at a descriptor it does not own

until the Am79C971 controller sets OWN to 0 to release

ownership to the software. (When LAPPEN (CSR3, bit

5) is set to 1, this rule is modified. See the LAPPEN de-

scription. At initialization, the Am79C971 controller

reads the base address of both the transmit and re-

ceive descriptor rings into CSRs for use by the

Am79C971 controller during subsequent operations.

Figure 31 illustrates the relationship between the initial-

ization base address, the initialization block, the re-

ceive and transmit descriptor ring base addresses, the

receive and transmit descriptors, and the receive and

transmit data buffers, when SSIZE32 is cleared to 0.

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