AM79C971VCW datasheet(72/265 Pages) AMD

72 / 265 page

Am79C971

The time delay from the last rising edge of the message

to IRXEN deassert allows the last bit to be strobed by

IRXCLK and transferred to the controller section, but

prevents any extra bit(s) at the end of message.

Data Decoding

The data receiver is a comparator with clocked output

to minimize noise sensitivity to the DI

± inputs. Input

error is less than

±35 mV to minimize sensitivity to input

rise and fall time. IRXCLK strobes the data receiver

output at 1/4 bit time to determine the value of the

Manchester bit, and clocks the data out on IRXDAT on

the following IRXCLK. The data receiver also gener-

ates the signal used for phase detector comparison to

the internal MENDEC VCO.

Jitter Tolerance Definition

The MENDEC utilizes a clock capture circuit to align its

internal data strobe with an incoming bit stream. The

clock acquisition circuitry requires four valid bits with

the values 1010b. The clock is phase-locked to the neg-

ative transition at the bit cell center of the second zero

in the pattern.

Since data is strobed at 1/4 bit time, Manchester tran-

sitions which shift from their nominal placement

through 1/4 bit time will result in improperly decoded

data. With this as the criterion for an error, a definition

of Jitter Handling is:

The peak deviation approaching or crossing 1/4 bit

cell position from nominal input transition, for which

the MENDEC section will properly decode data.

Attachment Unit Interface

The Attachment Unit Interface (AUI) is the PLS (Physi-

cal Layer Signaling) to PMA (Physical Medium Attach-

ment) interface which effectively connects the DTE to a

MAU. The differential interface provided by the

Am79C971 controller is fully compliant to Section 7 of

ISO 8802-3 (ANSI/IEEE 802.3) standard.

After the Am79C971 controller initiates a transmission

it will expect to see data “looped-back” on the DI

± pair

(when the AUI port is selected). This will internally gen-

erate a “carrier sense,” indicating that the integrity of

the data path to and from the MAU is intact, and that the

MAU is operating correctly. This “carrier sense” signal

must be asserted before end of transmission. If “carrier

sense” does not become active in response to the data

transmission, or becomes inactive before the end of

transmission, the loss of carrier (LCAR) error bit will be

set in the transmit descriptor ring (TMD2, bit 27) after

the frame has been transmitted.

Differential Input Termination

The differential input for the Manchester data (DI

±) is

externally terminated by two 40.2-

Ω resistors and one

optional common-mode bypass capacitor, as shown in

Figure 36. The differential input impedance, ZIDF, and

the common-mode input impedance, ZICM, are speci-

fied so that the Ethernet specification for cable termina-

tion impedance is met using standard 1% resistor

terminators. If SIP devices are used, 39 ohms is also a

suitable value. The CI

± differential inputs are termi-

nated in exactly the same way as the DI

± pair.

Figure 36.

AUI Differential Input Termination

Collision Detection

A MAU detects the collision condition on the network

and generates a 10-MHz differential signal at the CI

inputs. This collision signal passes through an input

stage which detects signal levels and pulse duration.

When the signal is detected by the MENDEC, it sets the

ICLSN line HIGH. The condition continues for approxi-

mately 1.5 bit times after the last LOW-to-HIGH transi-

tion on CI

±.

Twisted-Pair Transceiver

This section describes operation of the Twisted-Pair

Transceiver (T-MAU) when operating in half-duplex

mode. When in half-duplex mode, the T-MAU imple-

ments the MAU functions for the Twisted Pair Medium

as specified by the supplement to the IEEE 802.3 stan-

dard (Type 10BASE-T). When operating in full-duplex

mode, the MAC engine behavior changes as described

in the section Full-Duplex Operation.

The T-MAU provides twisted pair driver and receiver cir-

cuits, including on-board transmit digital predistortion

and receiver squelch, and a number of additional fea-

tures including Link Status indication, Automatic

Twisted Pair Receive Polarity Detection/Correction and

Indication, Receive Carrier Sense, Transmit Active, and

Collision Present indication.

Twisted Pair Transmit Function

The differential driver circuitry in the TXD

± and TXP±

pins provides the necessary electrical driving capability

and the pre-distortion control for transmitting signals

over maximum length Twisted Pair cable, as specified

by the 10BASE-T supplement to the ISO 8802-3 (IEEE/

Am79C971

DI+

DI-

40.2

Ω

40.2

Ω

0.01

µF

0.1

µF

AUI Isolation

Transformer

20550D-39

AM79C971VCW 数据表(PDF) 72 Page - Advanced Micro Devices

AM79C971VCW 数据表(HTML) 72 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载