AM79C971VCW datasheet(66/265 Pages) AMD

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Am79C971

Receive Operation

The receive operation and features of the Am79C971

controller are controlled by programmable options. The

Am79C971 controller offers a large receive FIFO to

provide frame buffering for increased system latency,

automatic flushing of collision fragments (runt packets),

automatic receive pad stripping, and a variety of ad-

dress match options.

Receive Function Programming

Automatic pad field stripping is enabled by setting the

ASTRP_RCV bit in CSR4. This can provide flexibility in

the reception of messages using the IEEE 802.3 frame

format.

All receive frames can be accepted by setting the

PROM bit in CSR15. Acceptance of unicast and broad-

cast frames can be individually turned off by setting the

DRCVPA or DRCVBC bits in CSR15. The Physical Ad-

dress register (CSR12 to CSR14) stores the address

that the Am79C971 controller compares to the destina-

tion address of the incoming frame for a unicast ad-

dress match. The Logical Address Filter register

(CSR8 to CSR11) serves as a hash filter for multicast

address match.

The point at which the BMU will start to transfer data

from the receive FIFO to buffer memory is controlled by

the RCVFW bits in CSR80. The default established

during H_RESET is 01b, which sets the watermark flag

at 64 bytes filled.

For test purposes, the Am79C971 controller can be

programmed to accept runt packets by setting RPA in

CSR124.

Address Matching

The Am79C971 controller supports three types of ad-

dress matching: unicast, multicast, and broadcast. The

normal address matching procedure can be modified

by programming three bits in CSR15, the mode register

(PROM, DRCVPA, and DRCVBC).

If the first bit received after the SFD (the least signifi-

cant bit of the first byte of the destination address field)

is 0, the frame is unicast, which indicates that the frame

is meant to be received by a single node. If the first bit

received is 1, the frame is multicast, which indicates

that the frame is meant to be received by a group of

nodes. If the destination address field contains all 1s,

the frame is broadcast, which is a special type of multi-

cast. Frames with the broadcast address in the destina-

tion address field are meant to be received by all nodes

on the local area network.

When a unicast frame arrives at the Am79C971 con-

troller, the controller will accept the frame if the destina-

tion address field of the incoming frame exactly

matches the 6-byte station address stored in the Phys-

ical Address registers (PADR, CSR12 to CSR14). The

byte ordering is such that the first byte received from

the network (after the SFD) must match the least signif-

icant byte of CSR12 (PADR[7:0]), and the sixth byte re-

ceived must match the most significant byte of CSR14

(PADR[47:40]).

When DRCVPA (CSR15, bit 13) is set to 1, the

Am79C971 controller will not accept unicast frames.

If the incoming frame is multicast, the Am79C971 con-

troller performs a calculation on the contents of the

destination address field to determine whether or not to

accept the frame. This calculation is explained in the

section that describes the Logical Address Filter

(LADRF).

When all bits of the LADRF registers are 0, no multicast

frames are accepted, except for broadcast frames.

Although broadcast frames are classified as special

multicast frames, they are treated differently by the

Am79C971 controller hardware. Broadcast frames are

always accepted, except when DRCVBC (CSR15, bit

14) is set.

None of the address filtering described above applies

when the Am79C971 controller is operating in the pro-

miscuous mode. In the promiscuous mode, all properly

formed packets are received, regardless of the con-

tents of their destination address fields. The promiscu-

ous mode overrides the Disable Receive Broadcast bit

(DRCVBC bit l4 in the MODE register) and the Disable

Receive Physical Address bit (DRCVPA, CSR15, bit

13).

The Am79C971 controller operates in promiscuous

mode when PROM (CSR15, bit 15) is set.

In addition, the Am79C971 controller provides the Ex-

ternal Address Detection Interface (EADI) to allow ex-

ternal address filtering. See the section External

Address Detection Interface for further detail.

The receive descriptor entry RMD1 contains three bits

that indicate which method of address matching

caused the Am79C971 controller to accept the frame.

Note that these indicator bits are only available when

the Am79C971 controller is programmed to use 32-bit

structures for the descriptor entries (BCR20, bit 7-0,

SWSTYLE is set to 2 or 3).

PAM (RMD1, bit 22) is set by the Am79C971 controller

when it accepted the received frame due to a match of

the frame’s destination address with the content of the

physical address register.

LAFM (RMD1, bit 21) is set by the Am79C971 control-

ler when it accepted the received frame based on the

value in the logical address filter register.

BAM (RMD1, bit 20) is set by the Am79C971 controller

when it accepted the received frame because the

frame’s destination address is of the type ’Broadcast’.

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