EM357-RTR datasheet(158/241 Pages) SILABS

158 / 241 page

Rev 1.3

158

Bitname

Bitfield

Access

Description

TIM_OC4M

[14:12]

Output Compare 4 Mode. (Applies only if TIM_CC4S = 0.)

Define the behavior of the output reference signal OC4REF from which

OC4 derives. OC4REF is active high whereas OC4’s active level depends

on the TIM_CC4P bit.

000: Frozen - The comparison between the output compare register TIMx-

_CCR4 and the counter TIMx_CNT has no effect on the outputs.

001: Set OC4REF to active on match. The OC4REF signal is forced high

when the counter TIMx_CNT matches the capture/compare register 4

(TIMx_CCR4)

010: Set OC4REF to inactive on match. OC4REF signal is forced low

when the counter TIMx_CNT matches the capture/compare register 4

(TIMx_CCR4).

011: Toggle - OC4REF toggles when TIMx_CNT = TIMx_CCR4.

100: Force OC4REF inactive.

101: Force OC4REF active.

110: PWM mode 1 - In up-counting, OC4REF is active as long as

TIMx_CNT < TIMx_CCR4, otherwise OC4REF is inactive. In down-count-

ing, OC4REF is inactive if TIMx_CNT > TIMx_CCR4, otherwise OC4REF

is active.

111: PWM mode 2 - In up-counting, OC4REF is inactive if

TIMx_CNT < TIMx_CCR4, otherwise OC4REF is active. In down-count-

ing, OC4REF is active if TIMx_CNT > TIMx_CCR4, otherwise it is inac-

tive.

Note:

In PWM mode 1 or 2, the OC4REF level changes only when the result of

the comparison changes or when the output compare mode switches from

“frozen” mode to “PWM” mode.

TIM_OC4BE

[11]

Output Compare 4 Buffer Enable. (Applies only if TIM_CC4S = 0.)

0: Buffer register for TIMx_CCR4 is disabled. TIMx_CCR4 can be written

at anytime, the new value is used by the shadow register immediately.

1: Buffer register for TIMx_CCR4 is enabled. Read/write operations

access the buffer register. TIMx_CCR4 buffer value is loaded in the

shadow register at each UEV.

Note:

The PWM mode can be used without enabling the buffer register only in

one pulse mode (TIM_OPM bit set in the TIMx_CR2 register), otherwise

the behavior is undefined.

TIM_OC4FE

[10]

Output Compare 4 Fast Enable. (Applies only if TIM_CC4S = 0.)

This bit speeds the effect of an event on the trigger in input on the OC4

output.

0: OC4 behaves normally depending on the counter and TIM_CCR4 val-

ues even when the trigger is ON. The minimum delay to activate OC4

when an edge occurs on the trigger input is 5 clock cycles.

1: An active edge on the trigger input acts like a compare match on the

OC4 output. OC4 is set to the compare level independently from the result

of the comparison. Delay to sample the trigger input and to activate OC4

output is reduced to 3 clock cycles. TIM_OC4FE acts only if the channel is

configured in PWM 1 or PWM 2 mode.

EM357-RTR 数据表(PDF) 158 Page - Silicon Laboratories

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