TNETV6446AINZWT datasheet(102/227 Pages) TI1

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MXI/CLKIN

MXO

MXV

1.8V

MXV

TMS320DM6446

SPRS283H – DECEMBER 2005 – REVISED SEPTEMBER 2010

www.ti.com

6.5.2

Clock Input Option 2 – 1.8-V LVCMOS-Compatible Clock Input

In this option, a 1.8-V LVCMOS-compatible clock input is used as the external clock input to the DM6446

device. The external connections are shown in Figure 6-12. The MXI/CLKIN pin is connected to the 1.8-V

LVCMOS-compatible clock source. The MXO pin is left unconnected. The MXVSS pin is connected to

board ground (VSS). The MXVDD pin can be connected to the same 1.8-V power supply as DVDD18. The

clock source must meet the MXI/CLKIN timing requirements shown in Table 6-16, Timing Requirements

for MXI/CLKIN.

Figure 6-12. 1.8-V LVCMOS-Compatible Clock Input

Figure 6-12 also applies to the USB external clock input. When a 1.8-V LVCMOS-compatible clock input is

used as the external clock input, the M24XI pin is connected to the 1.8-V LVCMOS-compatible clock

source. The M24XO pin is left unconnected. The M24VSS pin is connected to board ground (VSS). The

M24VDD pin can be connected to the same 1.8-V power supply as DVDDR2. The clock source must meet

the MXI/CLKIN timing requirements shown in Table 6-17, Timing Requirements for M24XI (-594) Devices.

6.6

Clock PLLs

There are two independently controlled PLLs on DM6446. PLL1 generates the frequencies required for the

DSP, ARM, VICP, DMA, VPFE, and other peripherals. PLL2 generates the frequencies required for the

DDR2 interface and the VPBE in certain modes. The recommended reference clock for both PLLs is the

27-MHz crystal input. The USB2.0 PHY contains a third PLL embedded within it and the 24-MHz oscillator

is its reference clock source. This particular PLL is only usable for USB operation, and is discussed further

in the TMS320DM644x DMSoC Universal Serial Bus (USB) Controller User's Guide (literature number

SPRUE35).

A summary of the PLL controller registers is shown in Table 6-12. For more details, see the

TMS320DM644x DMSoC ARM Subsystem Reference Guide (literature number SPRUE14).

Table 6-12. PLL and Reset Controller Registers Memory Map

HEX ADDRESS RANGE

DESCRIPTION

PLL1 Controller Registers

0x01C4 0800

PID

Peripheral Identification and Revision Information Register

0x01C4 08E4

RSTYPE

Reset Type Register

0x01C4 0900

PLLC

PLL Controller 1 Operations Control Register

0x01C4 0910

PLLM

PLL Controller 1 Multiplier Control Register

0x01C4 0918

PLLDIV1

PLL Controller 1 Control-Divider 1 Register (SYSCLK1)

0x01C4 091C

PLLDIV2

PLL Controller 1 Control-Divider 2 Register (SYSCLK2)

0x01C4 0920

PLLDIV3

PLL Controller 1 Control-Divider 3 Register (SYSCLK3)

0x01C4 0928

POSTDIV

PLL Controller 1 Post-Divider Control Register

0x01C4 092C

BPDIV

PLL Controller 1 Bypass Control-Divider Register (SYSCLKBP)

0x01C4 0938

PLLCMD

PLL Controller 1 Command Register

0x01C4 093C

PLLSTAT

PLL Controller 1 Status Register (Shows PLLCTRL Status)

102

Peripheral and Electrical Specifications

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