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TNETV6446AINZWT 数据表(PDF) 103 Page - Texas Instruments |
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TNETV6446AINZWT 数据表(HTML) 103 Page - Texas Instruments |
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103 / 227 page  TMS320DM6446 www.ti.com SPRS283H – DECEMBER 2005 – REVISED SEPTEMBER 2010 Table 6-12. PLL and Reset Controller Registers Memory Map (continued) HEX ADDRESS RANGE REGISTER ACRONYM DESCRIPTION PLL Controller 1 Alignment Control Register 0x01C4 0940 ALNCTL (Indicates Which SYSCLKs Need to be Aligned for Proper Device Operation) PLL Controller 1 Divider Change Register 0x01C4 0944 DCHANGE (Indicates if SYSCLK Divide Ratio has Been Modified) 0x01C4 0948 CKEN PLL Controller 1 Clock Enable Register 0x01C4 094C CKSTAT PLL Controller 1 Clock Status Register (For All Clocks Except SYSCLKx) 0x01C4 0950 PLL Controller 1 System Clock Status 1 Register (Indicates SYSCLK on/off SYSTAT Status) 0x01C4 0960 PLLDIV4 PLL Controller 1 Control-Divider 4 Register (SYSCLK4) 0x01C4 0964 PLLDIV5 PLL Controller 1 Control-Divider 5 Register (SYSCLK5) 0x01C4 0C00 PID Peripheral Identification and Revision Information Register 0x01C4 0D00 PLLC PLL Controller 2 Operations Control Register 0x01C4 0D10 PLLM PLL Controller 2 Multiplier Control Register 0x01C4 0D18 PLLDIV1 PLL Controller 2 Control-Divider 1 Register (SYSCLK1) 0x01C4 0D1C PLLDIV2 PLL Controller 2 Control-Divider 2 Register (SYSCLK2) 0x01C4 0D20 - 0x01C4 0D2B POSTDIV PLL Controller 2 Post-Divider Control Register 0x01C4 0D2C BPDIV PLL Controller 2 Bypass Control-Divider Register (SYSCLKBP) 0x01C4 0D38 PLLCMD PLL Controller 2 Command Register 0x01C4 0D3C PLLSTAT PLL Controller 2 Status Register (Shows PLLCTRL Status) PLL Controller 2 Alignment Control Register 0x01C4 0D40 ALNCTL (Indicates Which SYSCLKs Need to be Aligned for Proper Device Operation) PLL Controller 2 Divider Change Register 0x01C4 0D44 DCHANGE (Indicates if SYSCLK Divide Ratio has Been Modified) 0x01C4 0D48 CKEN PLL Controller 2 Clock Enable Register 0x01C4 0D4C CKSTAT PLL Controller 2 Clock Status Register (For All Clocks Except SYSCLKx) 0x01C4 0D50 SYSTAT PLL Controller 2 System Clock Status 1 Register (Indicates SYSCLK on/off Status) 6.6.1 PLL1 and PLL2 Both PLL1 and PLL2 power is supplied externally via the 1.8 V PLL power-supply pin (PLLVDD18). It is recommended that an external EMI filter circuit be added to PLLVDD18, as shown in Figure 6-13. The 1.8-V supply of the EMI filter must be from the same 1.8-V power plane supplying the device’s 1.8-V I/O power-supply pins (DVDD). TI recommends EMI filter manufacturer Murata, part number NFM18CC222R1C3. All PLL external components (C1, C2, and the EMI Filter) should be placed as close to the device as possible. For the best performance, TI recommends that all the PLL external components be on a single side of the board without jumpers, switches, or components other than the ones shown in Figure 6-13. For reduced PLL jitter, maximize the spacing between switching signals and the PLL external components (C1, C2, and the EMI Filter). Copyright © 2005–2010, Texas Instruments Incorporated Peripheral and Electrical Specifications 103 Submit Documentation Feedback Product Folder Link(s): TMS320DM6446 |
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