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TNETV6446AINZWT 数据表(PDF) 107 Page - Texas Instruments |
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TNETV6446AINZWT 数据表(HTML) 107 Page - Texas Instruments |
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107 / 227 page  CLK_OUT0 (Divide-by-1) 1 2 4 4 CLKIN/MXI CLK_OUT0 (Divide-by-2) 5 6 7 8 3 TMS320DM6446 www.ti.com SPRS283H – DECEMBER 2005 – REVISED SEPTEMBER 2010 Table 6-18. Switching Characteristics Over Recommended Operating Conditions for CLK_OUT0(1) (2) (see Figure 6-16) A-513, -594, NO. PARAMETER UNIT -810 MIN MAX 1 tC Cycle time, CLK_OUT0 37.037 74.074 ns 2 tw(CLKOUT0H) Pulse duration, CLK_OUT0 high 0.45P 0.55P ns 3 tw(CLKOUT0L) Pulse duration, CLK_OUT0 low 0.45P 0.55P ns 4 tt(CLKOUT0) Transition time, CLK_OUT0 0.05P ns 5 td(CLKINH-CLKO0H) Delay time, CLKIN/MXI high to CLK_OUT0 high (divide-by-1 only) 1 8 ns 6 td(CLKINL-CLKO0L) Delay time, CLKIN/MXI low to CLK_OUT0 low (divide-by-1 only) 1 8 ns 7 td(CLKINH-CLKO0L) Delay time, CLKIN/MXI high to CLK_OUT0 low (divide-by-2 only) 1 8 ns 8 td(CLKINH-CLKO0H) Delay time, CLKIN/MXI high to CLK_OUT0 high (divide-by-2 only) 1 8 ns (1) The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN. (2) P = 1/CLK_OUT0 clock frequency in nanoseconds (ns). For example, when CLK_OUT0 frequency is 27 MHz, use P = 37.04 ns. Figure 6-16. CLK_OUT0 Timing Copyright © 2005–2010, Texas Instruments Incorporated Peripheral and Electrical Specifications 107 Submit Documentation Feedback Product Folder Link(s): TMS320DM6446 |
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