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PLLV

DD18

EMIFilter

+1.8V

DM644x

PLL2

PLL1

0.1µF

0.01µF

TMS320DM6446

SPRS283H – DECEMBER 2005 – REVISED SEPTEMBER 2010

www.ti.com

Figure 6-13. PLL1 and PLL2 External Connection

The minimum CLKIN rise and fall times should also be observed. For the input clock timing requirements,

see Section 6.6.3, Clock PLL Electrical Data/Timing (Input and Output Clocks).

There is an allowable range for PLL multiplier (PLLM). There is a minimum and maximum operating

frequency for MXI/CLKIN, PLLOUT, and the device clocks (SYSCLKs). The PLL Controllers must be

configured not to exceed any of these constraints documented in this section (certain combinations of

external clock inputs, internal dividers, and PLL multiply ratios might not be supported).

Table 6-13. PLLC1 Clock Frequency Ranges

CLOCK SIGNAL NAME

MIN

MAX

UNIT

MXI/CLKIN(1)

MHz

At 1.2-V CVDD

400

600

MHz

PLLOUT

At 1.3-V CVDD (-810 only)

400

810

MHz

-594 (commercial temp)

600

MHz

SYSCLK1 (CLKDIV1 Domain)

-810 (commercial temp)

810

MHz

A-513 (extended temp)

513

MHz

(1)

MXI/CLKIN input clock is used for both PLL Controllers (PLLC1 and PLLC2).

Table 6-14. PLLC2 Clock Frequency Ranges

CLOCK SIGNAL NAME

MIN

MAX

UNIT

MXI/CLKIN(1)

MHz

At 1.2-V CVDD

400

900

MHz

PLLOUT

At 1.3-V CVDD (-810 only)

400

900

MHz

(1)

MXI/CLKIN input clock is used for both PLL Controllers (PLLC1 and PLLC2).

Both PLL1 and PLL2 have stabilization, lock, and reset timing requirements that must be followed.

The PLL stabilization time is the amount of time that must be allotted for the internal PLL regulators to

become stable after the PLL is powered up (after PLLCTL.PLLPWRDN bit goes through a 1-to-0

transition). The PLL should not be operated until this stabilization time has expired. This stabilization step

must be applied after these resets—a Power-on Reset, a Warm Reset, or a Max Reset, as the

PLLCTL.PLLPWRDN bit resets to a "1". For the PLL stabliziation time value, see Table 6-15.

The PLL reset time is the amount of wait time needed for the PLL to properly reset (writing PLLRST = 0)

before bringing the PLL out of reset (writing PLLRST = 1). For the PLL reset time value, see Table 6-15.

104

Peripheral and Electrical Specifications

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