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数据搜索系统，热门电子元器件搜索 |
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ST7LITE49K2 数据表(PDF) 134 Page - STMicroelectronics |
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ST7LITE49K2 数据表(HTML) 134 Page - STMicroelectronics |
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134 / 245 page  On-chip peripherals ST7LITE49K2 134/245 Bit 4 = ICF2 Input capture flag 2 0: No input capture (reset value) 1: An input capture has occurred on the ICAP2 pin. To clear this bit, first read the SR register, then read or write the low byte of the IC2R (IC2LR) register. Bit 3 = OCF2 Output compare flag 2 0: No match (reset value) 1: The content of the free running counter has matched the content of the OC2R register. To clear this bit, first read the SR register, then read or write the low byte of the OC2R (OC2LR) register. Bit 2 = TIMD Timer disable This bit is set and cleared by software. When set, it freezes the timer prescaler and counter and disables the output functions (OCMP1 and OCMP2 pins) to reduce power consumption. Access to the timer registers is still available, allowing the timer configuration to be changed while it is disabled. 0: Timer enabled 1: Timer prescaler, counter and outputs disabled Bits 1:0 = Reserved, must be kept cleared Timer A input capture 1 high register (TAIC1HR) Reset value: undefined This is an 8-bit read-only register that contains the high part of the counter value (transferred by the input capture 1 event). Timer A input capture 1 low register (TAIC1LR) Reset value: undefined This is an 8-bit read-only register that contains the low part of the counter value (transferred by the input capture 1 event). 7 0 MSB LSB Read Only 7 0 MSB LSB Read Only |
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