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ST7LITE49K2 数据表(PDF) 132 Page - STMicroelectronics

部件名 ST7LITE49K2
功能描述  Communication interfaces
PDF  245 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

ST7LITE49K2 数据表(HTML) 132 Page - STMicroelectronics

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On-chip peripherals
ST7LITE49K2
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Bit 1 = IEDG1 Input edge 1
This bit determines which type of level transition on the ICAP1 pin triggers the capture.
0: A falling edge triggers the capture
1: A rising edge triggers the capture
Bit 0 = OLVL1 Output level 1
The OLVL1 bit is copied to the OCMP1 pin whenever a successful comparison occurs
with the OC1R register and the OC1E bit is set in the CR2 register.
Timer A
control register 2 (TACR2)
Reset value: 0000 0000 (00h)
Bit 7 = OC1E Output compare 1 pin enable
This bit is used only to output the signal from the timer on the OCMP1 pin (OLV1 in
output compare mode, both OLV1 and OLV2 in PWM and one-pulse mode). Whatever
the value of the OC1E bit, the output compare 1 function of the timer remains active.
0: OCMP1 pin alternate function disabled (I/O pin free for general-purpose I/O)
1: OCMP1 pin alternate function enabled
Bit 6 = 0C2E Output compare 2 pin enable
This bit is used only to output the signal from the timer on the OCMP2 pin (OLV2 in
output compare mode). Whatever the value of the OC2E bit, the output compare 2
function of the timer remains active.
0: OCMP2 pin alternate function disabled (I/O pin free for general-purpose I/O)
1: OCMP2 pin alternate function enabled
Bit 5 = OPM One pulse mode
0: One pulse mode is not active
1: One pulse mode is active, the ICAP1 pin can be used to trigger one pulse on
the OCMP1 pin; the active transition is given by the IEDG1 bit. The length of
the generated pulse depends on the contents of the OC1R register.
Bit 4 = PWM Pulse width modulation
0: PWM mode is not active
1: PWM mode is active, the OCMP1 pin outputs a programmable cyclic signal;
the length of the pulse depends on the value of OC1R register; the period
depends on the value of OC2R register.
Bits 3:2 CC[1:0] Clock control
The timer clock mode depends on the following bits:
00: Timer clock = fCPU/4
01: Timer clock = fCPU/2
7
0
OC1E
OC2E
OPM
PWM
CC[1:0]
IEDG2
EXEDG
Read / Write



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