ST7LITE49K2 datasheet(128/245 Pages) STMICROELECTRONICS

128 / 245 page

On-chip peripherals

ST7LITE49K2

128/245

Note:

There is a locking mechanism for transferring the OCiR value to the buffer. After a write to

the OCiHR register, transfer of the new compare value to the buffer is inhibited until OCiLR

is also written.

Unlike in output compare mode, the compare function is always enabled in PWM mode.

Procedure

To use pulse width modulation mode:

Load the OC2R register with the value corresponding to the period of the signal using

the formula in the opposite column.

Load the OC1R register with the value corresponding to the period of the pulse if

(OLVL1 = 0 and OLVL2 = 1) using Equation 5.

Select the following in the CR1 register:

Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after a successful

comparison with OC1R register.

Using the OLVL2 bit, select the level to be applied to the OCMP1 pin after a successful

comparison with OC2R register.

Select the following in the CR2 register:

Set OC1E bit: the OCMP1 pin is then dedicated to the output compare 1 function.

Set the PWM bit.

Select the timer clock (CC[1:0]) (see: Timer A control register 2 (TACR2) on page 132).

Figure 68.

Pulse width modulation cycle

If OLVL = 1 and OLVL2 = 0 the length of the positive pulse is the difference between the

OC2R and OC1R registers.

If OLVL1 = OLVL2 a continuous signal is seen on the OCMP1 pin.

counter

OCMP1 = OLVL2

OCMP1 = OLVL1

When

=OC1R

Pulse width modulation cycle

Counter is reset

to FFFCh

ICF1 bit is set

counter

When

= OC2R

ST7LITE49K2 数据表(PDF) 128 Page - STMicroelectronics

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