ST7LITE49K2 datasheet(129/245 Pages) STMICROELECTRONICS

129 / 245 page

ST7LITE49K2

On-chip peripherals

129/245

The OCiR register value required for a specific timing application can be calculated using

the following formula:

Equation 5

Where:

If the timer clock is an external clock the formula is:

Equation 6

Where:

The output compare 2 event causes the counter to be initialized to FFFCh (see Figure 67)

Note:

The OCF1 and OCF2 bits cannot be set by hardware in PWM mode therefore the output

compare interrupt is inhibited.

The ICF1 bit is set by hardware when the counter reaches the OC2R value and can produce

a timer interrupt if the ICIE bit is set and the I bit is cleared.

In PWM mode the ICAP1 pin can not be used to perform input capture because it is

disconnected to the timer. The ICAP2 pin can be used to perform input capture (ICF2 can be

set and IC2R can be loaded) but the user must take care that the counter is reset each

period and ICF1 can also generates interrupt if ICIE is set.

When the pulse width modulation (PWM) and one pulse mode (OPM) bits are both set, the

PWM mode is the only active one.

11.4.4

Low power modes

t =

signal or pulse period (in seconds)

fCPU =

CPU clock frequency (in hertz)

PRESC =

timer prescaler factor (2, 4 or 8 depending on CC[1:0] bits, see : Timer A control

t =

signal or pulse period (in seconds)

fEXT =

external timer clock frequency (in hertz)

OCiR value =

t * fCPU

PRESC

- 5

OCiR=

t * fEXT -5

Table 42.

Effect of low power modes on 16-bit timer

Mode

Description

Wait

No effect on 16-bit timer.

Timer interrupts cause the device to exit from Wait mode.

Halt

16-bit timer registers are frozen.

In Halt mode, the counter stops counting until Halt mode is exited. Counting resumes from

the previous count when the device is woken up by an interrupt with ‘exit from Halt mode’

capability or from the counter reset value when the device is woken up by a reset.

If an input capture event occurs on the ICAPi pin, the input capture detection circuitry is

armed. Consequently, when the device is woken up by an interrupt with ‘exit from Halt

mode’ capability, the ICFi bit is set, and the counter value present when exiting from Halt

mode is captured into the ICiR register.

ST7LITE49K2 数据表(PDF) 129 Page - STMicroelectronics

ST7LITE49K2 数据表(HTML) 129 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载