ST7LITE49K2 datasheet(131/245 Pages) STMICROELECTRONICS

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ST7LITE49K2

On-chip peripherals

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11.4.7

16-bit timer registers

Each timer is associated with three control and status registers, and with six pairs of data

registers (16-bit values) relating to the two input captures, the two output compares, the

counter and the alternate counter.

TIMA control register 1 (TACR1)

Reset value: 0000 0000 (00h)

Bit 7 = ICIE Input capture interrupt enable

0: Interrupt is inhibited

1: A timer interrupt is generated whenever the ICF1 or ICF2 bit of the SR register is

set

Bit 6 = OCIE Output compare interrupt enable

0: Interrupt is inhibited

1: A timer interrupt is generated whenever the OCF1 or OCF2 bit of the SR register is

set

Bit 5 = TOIE Timer overflow interrupt enable

0: Interrupt is inhibited

1: A timer interrupt is enabled whenever the TOF bit of the SR register is set

Bit 4 = FOLV2 Forced output compare 2

This bit is set and cleared by software.

0: No effect on the OCMP2 pin

1: Forces the OLVL2 bit to be copied to the OCMP2 pin, if the OC2E bit is set and

even if there is no successful comparison

Bit 3 = FOLV1 Forced output compare 1

This bit is set and cleared by software.

0: No effect on the OCMP1 pin

1: Forces OLVL1 to be copied to the OCMP1 pin, if the OC1E bit is set and even if

there is no successful comparison

Bit 2 = OLVL2 Output level 2

This bit is copied to the OCMP2 pin whenever a successful comparison occurs with the

OC2R register and OCxE is set in the CR2 register. This value is copied to the OCMP1

pin in one pulse mode and pulse width modulation mode.

ICIE

OCIE

TOIE

FOLV2

FOLV1

OLVL2

IEDG1

OLVL1

Read / Write

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