ST7LITE49K2 datasheet(145/245 Pages) STMICROELECTRONICS

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ST7LITE49K2

On-chip peripherals

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Master transmitter

Following the address transmission and after SR1 register has been read, the master

sends bytes from the DR register to the SDA line via the internal shift register.

The master waits for a read of the SR1 register followed by a write in the DR register,

holding the SCL line low (see Figure 71 Transfer sequencing EV8).

When the acknowledge bit is received, the interface sets EVF and BTF bits with an interrupt

if the ITE bit is set.

To close the communication: after writing the last byte to the DR register, set the STOP bit to

generate the Stop condition. The interface goes automatically back to slave mode (M/SL bit

cleared).

Error cases

●

BERR: Detection of a Stop or a Start condition during a byte transfer. In this case, the

EVF and BERR bits are set by hardware with an interrupt if ITE is set.

Note that BERR will not be set if an error is detected during the first pulse of each 9-bit

transaction:

Single Master mode

If a Start or Stop is issued during the first pulse of a 9-bit transaction, the BERR flag will

not be set and transfer will continue however the BUSY flag will be reset. To work

around this, slave devices should issue a NACK when they receive a misplaced Start or

Stop. The reception of a NACK or BUSY by the master in the middle of communication

gives the possibility to reinitiate transmission.

Multimaster mode

Normally the BERR bit would be set whenever unauthorized transmission takes place

while transfer is already in progress. However, an issue will arise if an external master

generates an unauthorized Start or Stop while the I2C master is on the first pulse of a

9-bit transaction. It is possible to work around this by polling the BUSY bit during I2C

master mode transmission. The resetting of the BUSY bit can then be handled in a

similar manner as the BERR flag being set.

●

AF: Detection of a non-acknowledge bit. In this case, the EVF and AF bits are set by

hardware with an interrupt if the ITE bit is set. To resume, set the Start or Stop bit.

The AF bit is cleared by reading the I2CSR2 register. However, if read before the

completion of the transmission, the AF flag will be set again, thus possibly generating a

new interrupt. Software must ensure either that the SCL line is back at 0 before reading

the SR2 register, or be able to correctly handle a second interrupt during the 9th pulse

of a transmitted byte.

●

ARLO: Detection of an arbitration lost condition.

In this case the ARLO bit is set by hardware (with an interrupt if the ITE bit is set and

the interface goes automatically back to slave mode (the M/SL bit is cleared).

Note:

In all these cases, the SCL line is not held low; however, the SDA line can remain low if the

last bits transmitted are all 0. It is then necessary to release both lines by software. The SCL

line is not held low while AF=1 but by other flags (SB or BTF) that are set at the same time.

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