ST7LITE49K2 datasheet(148/245 Pages) STMICROELECTRONICS

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On-chip peripherals

ST7LITE49K2

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11.5.7

I2C control register (I2CCR)

Reset value: 0000 0000 (00h)

Bits 7:6 = Reserved. Forced to 0 by hardware.

Bit 5 = PE Peripheral Enable bit

This bit is set and cleared by software.

0: Peripheral disabled

1: Master/Slave capability

Note:

When PE=0, all the bits of the CR register and the SR register except the Stop bit are reset.

All outputs are released while PE=0

When PE=1, the corresponding I/O pins are selected by hardware as alternate functions.

To enable the I2C interface, write the CR register TWICE with PE=1 as the first write only

activates the interface (only PE is set).

Bit 4 = ENGC Enable General Call bit

This bit is set and cleared by software. It is also cleared by hardware when the interface

is disabled (PE=0). The 00h General Call address is acknowledged (01h ignored).

0: General Call disabled

1: General Call enabled

Note:

In accordance with the I2C standard, when GCAL addressing is enabled, an I2C slave can

only receive data. It will not transmit data to the master.

Bit 3 = START Generation of a Start condition bit. This bit is set and cleared by software. It

is also cleared by hardware when the interface is disabled (PE=0) or when the Start

condition is sent (with interrupt generation if ITE=1).

●

In master mode:

0: No start generation

1: Repeated start generation

●

In slave mode:

0: No start generation

1: Start generation when the bus is free

Bit 2 = ACK Acknowledge enable bit

This bit is set and cleared by software. It is also cleared by hardware when the interface

is disabled (PE=0).

0: No acknowledge returned

1: Acknowledge returned after an address byte or a data byte is received

ENGC

START

ACK

STOP

ITE

Read / Write

ST7LITE49K2 数据表(PDF) 148 Page - STMicroelectronics

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