ST7LITE49K2 datasheet(147/245 Pages) STMICROELECTRONICS

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ST7LITE49K2

On-chip peripherals

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subsequent EV4 is not seen.

EV4: EVF=1, STOPF=1, cleared by reading SR2 register.

EV5: EVF=1, SB=1, cleared by reading SR1 register followed by writing DR register.

EV6: EVF=1, cleared by reading SR1 register followed by writing CR register (for example PE=1).

EV7: EVF=1, BTF=1, cleared by reading SR1 register followed by reading DR register.

10. EV8: EVF=1, BTF=1, cleared by reading SR1 register followed by writing DR register.

11. EV9: EVF=1, ADD10=1, cleared by reading SR1 register followed by writing DR register.

11.5.5

Low power modes

11.5.6

Interrupts

Figure 72.

Event flags and interrupt generation

Table 46.

Effect of low power modes on the I2C interface

Mode

Description

Wait

No effect on I2C interface.

I2C interrupts cause the device to exit from Wait mode.

Halt

I2C registers are frozen.

In Halt mode, the I2C interface is inactive and does not acknowledge data on the bus. The

I2C interface resumes operation when the MCU is woken up by an interrupt with “exit from

Halt mode” capability.

Table 47.

Description of interrupt events

Interrupt event(1)

The I2C interrupt events are connected to the same interrupt vector (see Interrupts chapter).

They generate an interrupt if the corresponding Enable Control Bit is set and the I-bit in the CC register is

reset (RIM instruction).

Event

flag

Enable

control

bit

Exit

from

Wait

Exit

from

Halt

10-bit Address Sent Event (Master mode)

ADD10

ITE

Yes

End of byte Transfer Event

BTF

Yes

Address Matched Event (Slave mode)

ADSL

Yes

Start Bit Generation Event (Master mode)

Yes

Acknowledge Failure Event

Yes

Stop Detection Event (Slave mode)

STOPF

Yes

Arbitration Lost Event (Multimaster configuration)

ARLO

Yes

Bus Error Event

BERR

Yes

BTF

ADSL

STOPF

ARLO

BERR

EVF

INTERRUPT

ITE

* EVF can also be set by EV6 or an error from the SR2 register.

ADD10

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