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ST7LITE49K2 数据表(PDF) 181 Page - STMicroelectronics

部件名 ST7LITE49K2
功能描述  Communication interfaces
PDF  245 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

ST7LITE49K2 数据表(HTML) 181 Page - STMicroelectronics

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Comparator control register (CMPxCR)
Reset Value: 1000 0000 (80h)
Bit 7 = CHYST Comparator hysteresis enable
This bit is set or cleared by software and set by hardware reset. When this bit is set, the
comparator hysteresis is enabled.
0: Hysteresis disabled
1: Hysteresis enabled
Note:
To avoid spurious toggling of the output of the comparator due to noise on the voltage
reference, it is recommended to enable the hysteresis.
Bit 6 = Reserved, Must be kept cleared
Bit 5 = CINV Comparator output inversion select
This bit is set or cleared by software and cleared by hardware reset. When this bit is set, the
comparator output is inverted.
If interrupt enable bit CMPIE is set in the CMPCR register, the CINV bit is also used to select
which type of level transition on the comparator output will generate the interrupt. When this
bit is reset, interrupt will be generated at the rising edge of the comparator output change
(COMP signal, refer to Figure 82 on page 179). When this bit is set, interrupt will be
generated at the falling edge of comparator output change (COMP signal, refer to Figure 82
on page 179).
0: Comparator output not inverted and interrupt generated at the rising edge of COMP
1: Comparator output inverted and interrupt generated at the falling edge of COMP
Bit 4 = CMPIF Comparator interrupt flag
This bit is set by hardware when interrupt is generated at the rising edge (CINV = 0) or
falling edge (CINV = 1) of comparator output. This bit is cleared by reading the CMPCR
register. Writing to this bit does not change the value.
0 : Comparator interrupt flag cleared
1 : Comparator interrupt flag set and can generate interrupt if CMPIE is set.
Bit 3 : CMPIE Comparator interrupt enable
This bit is set or reset by software and cleared by hardware reset. This bit enables or
disables the interrupt generation depending on interrupt flag
0: Interrupt not generated
1: Interrupt generated if interrupt flag is set
7
0
CHYST
0
CINV
CMPIF
CMPIE
CMP
COUT
CMPON
Read/write



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