ST7LITE49K2 datasheet(226/245 Pages) STMICROELECTRONICS

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Electrical characteristics

ST7LITE49K2

226/245

Figure 123. RESET pin protection when LVD is disabled

The reset network protects the device against parasitic resets.

The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad.

Otherwise the device can be damaged when the ST7 generates an internal reset (LVD or watchdog).

Whatever the reset source is (internal or external), the user must ensure that the level on the RESET pin

can go below the VIL max. level specified in Section 13.10.1 on page 224. Otherwise the reset will not be

taken into account internally.

Because the reset circuit is designed to allow the internal Reset to be output in the RESET pin, the user

must ensure that the current sunk on the RESET pin is less than the absolute maximum value specified for

IINJ(RESET) in Section Table 70. on page 194.

Please refer to Section 12.2.1 on page 189 for more details on illegal opcode reset conditions.

13.11

10-bit ADC characteristics

Subject to general operating condition for VDD, fOSC, and TA unless otherwise specified.

0.01

μF

EXTERNAL

RESET

CIRCUIT

USER

Required

ST7XXX

PULSE

GENERATOR

Filter

RON

VDD

INTERNAL

RESET

WATCHDOG

ILLEGAL OPCODE

Table 99.

ADC characteristics

Symbol

Parameter

Conditions

Min

Typ(1)

Max

Unit

fADC

ADC clock frequency(2)

4MHz

VAIN

Conversion voltage range

VSSA

VDDA

RAIN

External input resistor

VDD = 5 V, fADC = 4 MHz

8k(3)

VDD = 3.3 V, fADC = 4 MHz

7k(3)

2.7 V

≤VDD ≤5.5 V, f

ADC = 2 MHz

10k(3)

2.4 V

≤VDD ≤2.7 V, f

ADC = 1 MHz

20k(3)

CADC

Internal sample and hold

capacitor

6pF

tSTAB

Stabilization time after ADC

enable

CPU = 8 MHz, fADC = 4 MHz

0(4)

μs

tADC

Conversion time (Sample+Hold)

3.5

- Sample capacitor loading time

- Hold conversion time

1/fADC

Unless otherwise specified, typical data are based on TA = 25 °C and VDD-VSS = 5 V. They are given only as design

guidelines and are not tested.

The maximum ADC clock frequency allowed within VDD = 2.4 V to 2.7 V operating range is 1 MHz.

Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than the maximum

value). Data guaranteed by Design, not tested in production.

The stabilization time of the A/D converter is masked by the first tLOAD. The first conversion after the enable is then always

valid.

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