DSP56303 datasheet(283/292 Pages) FREESCALE

283 / 292 page

DSP56303 User’s Manual, Rev. 2

Freescale Semiconductor

Index-5

Index

general-purpose flags for host-DSP communication 6-6

General-Purpose Input/Output (GPIO) 1-12

, 2-2, 2-17

functions 6-3

Host Data Direction Register (HDDR) 6-12

, 6-30

Host Data Register (HDR) 6-12

, 6-30

Port B 5-6

Port C 5-7

Port D 5-7

Port E 5-7

Global Data Bus (GDB) 1-10

Ground 2-3

PLL 2-3

HACK signal 6-18

handshaking mechanisms

HI08 6-5

hardware stack 1-8

HI08 1-12

ISR

Transmit Data Register Empty 6-25

HI08 Interrupt Priority Level (HPL) bits 4-16

Host Acknowledge Enable (HAEN) bit 6-18

Host Acknowledge Polarity (HAP) bit 6-16

Host Address Line 8 Enable (HA8EN) 6-18

Host Address Line 9 Enable (HA9EN) 6-18

, 7-19

Host Address Strobe Polarity (HASP) bit 6-17

Host Base Address Register (HBAR) 6-12

, 6-15, 6-30

programming sheet B-19

Host Chip Select Enable (HCSEN) bit 6-18

Host Chip Select Polarity (HSCP) bit 6-17

Host Command (HC) bit 6-24

Host Command Interrupt Enable (HCIE) bit 6-13

Host Command Pending (HCP) bit 6-14

Host Control Register (HCR) 6-12

, 6-28

Host Command Interrupt Enable (HCIE) 6-13

Host Flags 2,3 (HF) 6-12

Host Receive Interrupt Enable (HRIE) 6-13

Host Transmit Interrupt Enable (HTIE) 6-13

programming sheet B-20

Host Data Direction Register (HDDR) 6-3

, 6-12, 6-14

programming sheet B-31

Host Data Direction Register (HDRR) 6-30

Host Data Register (HDR) 6-12

, 6-15, 6-30

programming sheet B-31

Host Data Strobe Polarity (HDSP) bit 6-17

Host Dual Data Strobe (HDDS) bit 6-17

Host Enable (HEN) bit 6-17

Host Flag 0 (HF0) bit 6-23

Host Flag 1 (HF1) bit 6-23

Host Flag 2 (HF2) bit 6-25

Host Flag 3 (HF3) bit 6-25

Host Flags 0, 1 (HF) bits 6-14

Host Flags 2,3 (HF) bits 6-12

Host GPIO Port Enable (HGEN) bit 6-18

Host Interface (HI08) 2-2

, 2-9, 2-10, 2-12, 6-1

chip-select logic 6-16

Command Vector Register (CVR) 6-7

, 6-21

Host Command (HC) 6-24

Host Vector (HV) 6-24

programming sheet B-21

configuring host request mode 6-8

control operating mode 6-16

core communication with HI08 registers 6-11

core interrupts

host command 6-7

receive data register full 6-7

transmit data empty 6-7

data registers 6-21

data strobe 6-3

Direct Memory Access (DMA) 6-8

DMA transfers and host bus 6-8

double-buffered mechanism 6-5

DSP core 6-5

programming model 6-11

DSP core interrupts 6-6

DSP interrupt routines 6-21

DSP-side

control registers 6-12

data registers 6-12

registers after reset 6-20

DSP-to-host

data word 6-2

handshaking protocols 6-2

interrupts 6-2

mapping 6-2

transfer modes 6-2

transfers 6-5

, 6-19

dual host request enabled 6-9

dual-strobe mode 6-19

enabling host requests 6-8

external host address inputs 6-27

external host programmer’s model 6-20

four kinds of reset 6-27

four reset types 6-20

general-purpose flags for host-DSP communication 6-6

GPIO configuration options 6-14

GPIO functions 6-3

HACK signal 6-18

HACK/HRRQ handshake flags 6-21

handshaking mechanisms 6-5

handshaking protocols 6-5

choosing 6-6

Core DMA access 6-5

host request 6-5

interrupts 6-5

pros and cons of polling 6-6

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