DSP56303 datasheet(286/292 Pages) FREESCALE

286 / 292 page

DSP56303 User’s Manual, Rev. 2

Index-8

Freescale Semiconductor

Index

Interrupt Mask (I) bits 4-10

Interrupt Priority Register Core (IPRC) 4-15

IRQD–IRQA Priority and Mode (IDL–IAL) 4-15

Interrupt Priority Register Peripherals (IPRP) 4-15

, 4-16

ESSI0 Interrupt Priority Level (S0L) 4-16

ESSI1 Interrupt Priority Level (S1L) 4-16

HI08 Interrupt Priority Level (HPL) 4-16

SCI Interrupt Priority Level (SCL) 4-16

Timer Interrupt Priority Level (TOL) 4-16

Interrupt Priority Register-Peripherals (IPR-P)

programming sheet B-12

interrupt routines

Host Interface (HI08) 6-7

Interrupt Service Routine (ISR) 7-8

, 9-4

interrupt trigger event 7-9

Interrupt Vector Register (IVR) 6-21

programming sheet B-22

Inverter (INV) bit 9-25

, 9-27

IRQD–IRQA Priority and Mode (IDL–IAL) bits 4-15

Joint Test Action Group (JTAG) 1-9

, 2-18, 4-34

Test Acces Port(TAP) 1-5

Limit (L) bit 4-10

Loop Address register (LA) 1-8

Loop Counter register (LC) 1-8

M68HC11 SCI interface 8-14

manual conventions 1-2

mapping control registers 5-1

MC68000 family 6-26

MC68681 DUART 8-14

memory

allocation switching 3-2

configuration 3-5

dynamic switching 3-5

expansion 3-1

external expansion port 1-10

maps 3-6

on-chip 1-9

Memory Expansion Port 1-5

memory map

internal I/O B-2

Memory Switch mode 3-2

X data Memory 3-3

X data memory 3-4

Memory Switch Mode (MS) bit 4-14

MODD, MODC, MODB, and MODA 8-7

mode control 2-8

Mode Register (MR) 4-7

Do Loop Flag (LF) 4-9

Double-Precision Multiply Mode (DM) 4-9

Interrupt Mask (I) 4-10

Scaling (S) Mode 4-10

Sixteen-Bit Compatibility (SC) mode 4-9

Mode Select (MOD) bit 7-20

move (MOVE, MOVEP) instructions 5-1

MOVEP instruction 6-12

Multidrop mode 8-2

multiplexed bus mode 2-2

, 6-3, 6-15, 6-18

Multiplication Factor (MF) bits 4-21

Multiplier-Accumulator (MAC) 1-6

Negative (N) bit 4-11

Network mode 7-7

non-multiplexed bus mode 2-2

, 6-3

off-chip memory 1-5

, 3-1

On-Chip Emulation (OnCE) module 1-5

, 1-9, 2-18

on-chip memory 1-5

, 1-9

On-Demand mode 7-9

, 7-14

operating frequency 1-5

operating mode 4-1

Host Interface (HI08) 6-16

Operating Mode Register (OMR) 1-8

, 4-12

Address Attribute Priority Disable (APD) 4-13

Address Trace Enable (ATE) 4-13

Asynchronous Bus Arbitration Enable (ABE) 4-13

Bus Release Timing (BRT) 4-13

Cache Burst Mode Enable (BE) 4-14

Chip Operating Mode (MD–MA) 4-14

COM byte 4-12

Core-DMA Priority (CDP) 4-14

EOM byte 4-12

External Bus Disable (EBD) 4-14

Memory Switch Mode (MS) 4-14

programming sheet B-11

SCS byte 4-12

Stack Extension Enable (SEN) 4-12

Stack Extension Overflow Flag (EOV) 4-12

Stack Extension Underflow Flag (EUN) 4-13

Stack Extension Wrap Flag (WRP) 4-12

Stack Extension XY Select (XYS) 4-13

Stop Delay Mode (SD) 4-14

TA Synchronize Select (TAS) 4-13

Overflow (V) bit 4-11

Overrun Error Flag (OR) bit 8-16

Parity Error (PE) bit 8-15

Peripheral I/O Expansion Bus 1-10

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