DSP56303 datasheet(284/292 Pages) FREESCALE

284 / 292 page

DSP56303 User’s Manual, Rev. 2

Index-6

Freescale Semiconductor

Index

software polling 6-5

hardware reset 6-20

, 6-27

HI08-to-DSP core interface 6-1

HI08-to-host

interface 6-1

Host Base Address Register (HBAR) 6-12

, 6-15, 6-30

programming sheet B-19

host command 6-7

, 6-21

Host Control Register (HCR) 6-12

, 6-28

Host Command Interrupt Enable (HCIE) 6-13

Host Flags 2, 3 (HF) 6-12

Host Receive Interrupt Enable (HRIE) 6-13

Host Transmit Interrupt Enable (HTIE) 6-13

programming sheet B-20

Host Data Direction Register (HDDR) 6-3

, 6-12, 6-14

programming sheet B-31

Host Data Direction Register (HDRR) 6-30

Host Data Register (HDR) 6-12

, 6-15, 6-30

programming sheet B-31

host interrupt request pins (IRQx) 6-8

Host Port Control Register (HPCR) 6-3

, 6-12, 6-16,

6-20

, 6-28, 6-29

Host Acknowledge Enable (HAEN) 6-18

Host Acknowledge Polarity (HAP) 6-16

Host Address Line 8 Enable (HA8EN) 6-18

Host Address Line 9 Enable (HA9EN) 6-18

, 7-19

Host Address Strobe Polarity (HASP) 6-17

Host Chip Select Enable (HCSEN) 6-18

Host Chip Select Polarity (HCSP) 6-17

Host Data Strobe Polarity (HDSP) 6-17

Host Dual Data Strobe (HDDS) 6-17

Host Enable (HEN) 6-17

Host GPIO Port Enable (HGEN) 6-18

Host Multiplexed Bus (HMUX) 6-17

Host Request Enable (HREN) 6-18

Host Request Open Drain (HROD) 6-17

Host Request Polarity (HRP) 6-16

programming sheet B-4

, B-19

host processor registers 6-12

Host Receive (HRX) register 6-5

, 6-19, 6-30

Host Receive Data Register (HRX) 6-19

Host Receive Request (HRRQ) 6-8

host request line 6-3

host request pins 6-9

host side

Command Vector Register (CVR) 6-24

Interface Control Register (ICR) 6-22

Interface Status Register (ISR) 6-24

Interface Vector Register (IVR) 6-26

Receive Byte Registers (RXH, RXM, RXL) 6-26

Transmit Byte Registers (TXH, TXM, TXL) 6-27

host side registers after reset 6-27

Host Status Register (HSR) 6-12

, 6-13, 6-30

Host Command Pending (HCP) 6-14

Host Flags 0, 1 (HF) 6-14

Host Receive Data Full (HRDF) 6-14

Host Transmit Data Empty (HTDE) 6-14

Host Transmit (HTX) register 6-6

, 6-19, 6-26, 6-30

Host Transmit Data Register (HTDR)

programming sheet B-18

, B-22

host-side

host-to-DSP

data transfers 6-5

, 6-19

data word 6-1

handshaking protocols 6-1

instructions 6-1

mapping 6-1

HREQ/HTRQ handshake flags 6-21

instructions and addressing modes. 6-4

Interface Control Register (ICR) 6-21

, 6-22

Double Host Request (HDRQ) 6-8

, 6-23

Host Flag 0 (HF0) 6-23

Host Flag 1 (HF1) 6-23

Host Little Endian (HLEND) 6-23

Initialize (INIT) 6-22

Receive Request Enable (RREQ) 6-23

Transmit Request Enable (TREQ) 6-23

Interface Status Register (ISR) 6-21

, 6-24

Host Flag 2 (HF2) 6-25

Host Flag 3 (HF3) 6-25

Host Request (HREQ) 6-25

Receive Data Full (RDF) 6-6

Receive Data Register Full (RXDF) 6-26

Transmit Data Empty (TDE) 6-6

Transmit Data Register Empty (TXDE) 6-25

Transmitter Ready (TRDY) 6-25

interrupt routines 6-7

Interrupt Vector Register (IVR) 6-21

, 6-26

programming sheet B-22

interrupt-based techniques 6-20

masking interrupts 6-7

MOVEP instruction 6-12

multiplexed bus mode 6-3

, 6-15, 6-18

non-multiplexed bus mode 6-3

, 6-18

pipeline 6-5

polling techniques 6-20

, 6-26

programming model

DSP side 6-11

host side 6-20

quick reference 6-28

Receive Byte Registers (RXH, RHM, RHL) 6-6

Receive Byte Registers (RXH, RXM, RXL) 6-5

, 6-26

request service from host 6-8

resets

hardware and software 6-3

, 6-12

single-strobe mode 6-19

software polling 6-6

software reset 6-27

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