DSP56303 datasheet(285/292 Pages) FREESCALE

285 / 292 page

DSP56303 User’s Manual, Rev. 2

Freescale Semiconductor

Index-7

Index

STOP command 6-21

STOP instruction 6-27

Stop mode 6-21

timing requirements 6-6

Transmit Byte Registers 6-5

Transmit Byte Registers (TXH, TXM, TXL) 6-27

Transmit Data Registers (TXH, TXM, TXL) 6-5

Transmit Registers (TXH, TXM, TXL) 6-6

vector registers 6-21

Host Litle Endian (HLEND) bit 6-23

Host Multiplexed Bus (HMUX) bit 6-17

host port

configuration 2-9

usage considerations 2-9

Host Port Control Register (HPCR) 6-3

, 6-12, 6-16, 6-20,

6-28

, 6-29

Host Acknowledge Enable (HAEN) 6-18

Host Acknowledge Polarity (HAP) 6-16

Host Address Line 8 Enable (HA8EN) 6-18

Host Address Line 9 Enable (HA9EN) 6-18

, 7-19

Host Address Strobe Polarity (HASP) 6-17

Host Chip Select Enable (HCSEN) 6-18

Host Chip Select Polarity (HCSP) 6-17

Host Data Strobe Polarity (HDSP) 6-17

Host Dual Data Strobe (HDDS) 6-17

Host Enable (HEN) 6-17

Host GPIO Port Enable (HGEN) 6-18

Host Multiplexed Bus (HMUX) 6-17

Host Request Enable (HREN) 6-18

Host Request Open Drain (HROD) 6-17

Host Request Polarity (HRP) 6-16

programming sheet B-4

, B-19

host processor address space 6-21

Host Receive (HRX) register 6-5

, 6-12, 6-19, 6-30

Host Receive Data Full (HRDF) bit 6-6

, 6-14

Host Receive Interrupt Enable (HRIE) bit 6-13

Host Receive Request (HRRQ) 6-8

host request 6-5

double 2-2

enabling 6-8

single 2-2

Host Request (HREQ) bit 6-25

Host Request Enable (HREN) bit 6-18

host request line 6-3

Host Request Open Drain (HROD) bit 6-17

host request pins 6-9

Host Request Polarity (HRP) bit 6-16

Host Status Register (HSR) 6-12

, 6-13, 6-30

Host Command Pending (HCP) 6-14

Host Flags 0, 1 (HF) 6-14

Host Receive Data Full (HRDF) 6-14

Host Transmit Data Empty (HTDE) 6-14

Host Transmit (HTX) register 6-6

, 6-12, 6-19, 6-30

Host Transmit Data Empty (HTDE) bit 6-6

, 6-14

Host Transmit Data Register (HTDR)

programming sheet B-18

, B-22

Host Transmit Interrupt Enable (HTIE) bit 6-13

Host Vector (HV) bits 6-24

Hosts Interface (HI08)

Interrupt Control Register (ICR)

programming sheet B-21

host-to-DSP transfers 6-5

I/O space

X data memory 3-3

, 3-4

Idle Line Flag (IDLE) bit 8-16

Idle Line Interrupt Enable (ILIE) bit 8-12

Idle Line Wakeup mode 8-3

Initialize (INIT) bit 6-22

initializing the timer 9-3

instruction cache 1-5

, 3-2

location 3-6

Interface Control Register (ICR) 6-22

Double Host Request (HDRQ) 6-8

, 6-23

Host Flag 0 (HF0) 6-23

Host Flag 1 (HF1) 6-23

Host Little Endian (HLEND) 6-23

Initialize (INIT) 6-22

Receive Request Enable (RREQ) 6-23

Transmit Request Enable (TREQ) 6-23

Interface Status Register (ISR) 6-24

Host Flag 2 (HF2) 6-25

Host Flag 3 (HF3) 6-25

Host Request (HREQ) 6-25

Receive Data Full (RDF) 6-6

Receive Data Register Full (RXDF) 6-26

Transmit Data Empty (TDE) 6-6

Transmit Data Register Empty (TXDE) 6-25

Transmitter Ready (TRDY) 6-25

Interface Vector Register (IVR) 6-26

internal buses 1-10

internal I/O memory map B-2

internal program memory 3-1

, 3-2

interrupt 1-8

, 5-2

configuring 4-15

Host Interface (HI08) 6-5

, 6-6

priorities B-8

source priorities 4-18

sources 4-15

, 4-16, B-6

table 4-15

table, memory map 4-16

trigger mode 4-16

vector 4-16

interrupt and mode control 2-8

interrupt conditions 5-2

interrupt control 2-8

Interrupt Control Register (ICR)

programming sheet B-21

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