DSP56303 datasheet(289/292 Pages) FREESCALE

289 / 292 page

DSP56303 User’s Manual, Rev. 2

Freescale Semiconductor

Index-11

Index

SCI Clock Control Register (SCCR) 8-6

, 8-7, 8-8, 8-17

bit definitions 8-17

Clock Divider (CD) 8-17

Clock Out Divider (COD) 8-17

Clock Prescaler (SCP) 8-17

programming sheet B-27

Receive Clock Mode Source (RCM) 8-17

Transmit Clock Source (TCM) 8-17

SCI Control Register (SCR) 8-6

, 8-7, 8-8, 8-10

bit defintions 8-11

Idle Line Interrupt Enable (ILIE) 8-12

programming sheet B-26

Receive with Exception Interrupt Enable

(REIE) 8-11

Receiver Enable (RE) 8-13

Receiver Wakeup Enable (RWU) 8-13

SCI Clock Polarity (SCKP) 8-11

SCI Receive Interrupt Enable (RIE) 8-12

SCI Shift Direction (SSFTD) 8-14

SCI Transmit Interrupt Enable (TIE) 8-12

Send Break (SBK) 8-14

Timer Interrupt Enable (TMIE) 8-11

Timer Interrupt Rate (STIR) 8-11

Transmitter Enable (TE) 8-12

Wakeup Mode Select (WAKE) 8-13

Wired-OR Mode Select (WOMS) 8-13

Word Select (WDS) 8-14

SCI Receive Data Register (SRX) 8-8

, 8-20

SCI Status Register (SSR) 8-8

, 8-15

bit definitions 8-15

Framing Error Flag (FE) 8-15

Idle Line Flag (IDLE) 8-16

Overrun Error Flag (OR) 8-16

Parity Error (PE) 8-15

Receive Data Register Full (RDRF) 8-16

Received Bit 8 (R8) 8-15

Transmit Data Register Empty (TDRE) 8-16

Transmitter Empty (TRNE) 8-16

SCI Transmit Data Address Register (STXA) 8-9

SCI Transmit Data Register (STX) 8-8

select wakeup on idle line mode 8-13

Serial Clock (SCLK) 8-4

, 8-19

state after reset 8-5

Synchronous mode 8-2

transmission priority

preamble, break, and data 8-7

transmit and receive shift registers 8-2

Transmit Data (TXD) 8-4

Transmit Data Register (STX or STXA) 8-19

Transmit Data Register (STX) 8-21

Wired-OR mode 8-3

Serial Control 0 (SC00 and SC10) signals 7-3

Serial Control 1 (SC01 and SC11) signals 7-4

Serial Control 2 (SC02 and SC12) signals 7-5

Serial Control Direction 0 (SCD0) bit 7-22

Serial Control Direction 1 (SCD1) bit 7-22

Serial Control Direction 2 (SCD2) bit 7-21

Serial Input Flag 0 (IF0) bit 7-4

, 7-28

Serial Input Flag 1 (IF1) bit 7-28

Serial Output Flag (OF0–OF1) bits 7-17

Serial Output Flag 0 (OF0) bit 7-4

, 7-22

Serial Output Flag 1 (OF1) bit 7-22

Serial Receive Data (SRD) signal 7-3

Serial Transmit Data (STD) signal 7-2

setting timer operating mode 9-3

Shift Direction (SHFD) bit 7-21

signals 2-1

signals, functional groups 2-2

single data strobe mode 2-2

Sixteen-Bit Arithmetic Mode (SA) bit 4-8

Sixteen-Bit Compatibility (SC) mode bit 4-9

Sixteen-bit Compatibility mode 3-5

Size register (SZ) 1-8

software polling 6-5

SRAM, interfacing 1-10

Stack Counter register (SC) 1-8

Stack Extension Enable (SEN) bit 4-12

Stack Extension Overflow Flag (EOV) bit 4-12

Stack Extension Underflow Flag (EUN) bit 4-13

Stack Extension Wrap Flag (WRP) bit 4-12

Stack Extension XY Select (XYS) bit 4-13

Stack Pointer (SP) 1-8

standby mode

Stop 1-5

Wait 1-5

Status Register (SR) 1-8

, 4-7, 4-8

bit definitions 4-8

Condition Code Register (CCR) 4-7

Carry (C) 4-11

Extension (E) 4-11

Limit (L) 4-10

Negative (N) 4-11

Overflow (V) 4-11

Scaling (S) 4-10

Unnormalized (U) 4-11

Zero (Z) 4-11

Extended Mode Register (EMR) 4-7

Arithmetic Saturation Mode (SM) 4-8

Cache Enable (CE) 4-8

Core Priority (CP) 4-7

, 4-8

DO FOREVER (FV) Flag 4-9

Instruction Cache Enable (CE) 4-7

Rounding Mode (RM) 4-8

Sixteen-Bit Arithmetic Mode (SA) 4-8

Mode Register (MR) 4-7

Do Loop Flag (LF) 4-9

Double-Precision Multiply Mode (DM) 4-9

Interrupt Mask (I) 4-10

Scaling (S) Mode 4-10

Sixteen-Bit Compatibility (SC) Mode 4-9

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