DSP56303 datasheet(291/292 Pages) FREESCALE

291 / 292 page

DSP56303 User’s Manual, Rev. 2

Freescale Semiconductor

Index-13

Index

Prescaler Counter Value (PC) 9-23

Timer Prescaler Load Register (TPLR) 9-4

, 9-22

bit definitions 9-23

Prescaler Preload Value (PL) 9-23

Prescaler Source (PS) 9-23

programming sheet B-28

Timer Reload Mode (TRM) bit 9-25

Transmit 0 Enable (TE0) bit 7-19

Transmit 1 Enable (TE1) bit 7-19

Transmit 2 Enable (TE2) bit 7-20

Transmit Byte Registers (TXH, TXM, TXL) 6-5

, 6-27

Transmit Clock Source (TDM) bit 8-17

Transmit Data Empty (TDE) bit 6-6

Transmit Data Register Empty (TDE) bit 7-27

Transmit Data Register Empty (TDRE) bit 8-16

Transmit Data Register Empty (TXDE) bit 6-25

Transmit Data Registers (TX0–TX2) 7-12

, 7-31

Transmit Data Registers (TXH, TXM, TXL) 6-5

Transmit Data signal (TXD) 8-4

Transmit Enable (TE) bits 7-17

Transmit Exception Interrupt Enable (TEIE) bit 7-18

Transmit Frame Sync Flag (TFS) 7-27

Transmit Interrupt Enable (TIE) bit 7-18

Transmit Last Slot Interrupt Enable (TLIE) bit 7-18

Transmit Request Enable (TREQ) bit 6-23

Transmit Shift Registers 7-28

Transmit Slot Mask Registers (TSMA and TSMB) 7-12

7-31

Transmitter Empty (TRNE) bit 8-16

Transmitter Enable (TE) bit 8-12

Transmitter Ready (TRDY) bit 6-25

Transmitter Underrun Error Flag (TUE) 7-27

triple timer module 1-13

TX clock 7-10

TXD signal 8-4

TXH, TXM, TXL registers 6-27

Unnormalized (U) bit 4-11

Vector Base Address register (VBA) 1-8

Wait standby mode 1-5

Wakeup Mode Select (WAKE) bit 8-13

Wired-OR Mode Select (WOMS) bit 8-13

Word Length Control (WL) bits 7-14

Word Select (WDS) bits 8-14

X data memory 1-5

, 3-3

X I/O space 3-3

, 3-4

X Memory Address Bus (XAB) 1-10

X Memory Data Bus (XDB) 1-10

X Memory Expansion Bus 1-10

XTAL Disable (XTLD) bit 4-20

Y data memory 1-5

, 3-4

Y Memory Address Bus (YAB) 1-10

Y Memory Data Bus (YDB) 1-10

Y Memory Expansion Bus 1-10

Zero (Z) bit 4-11

DSP56303 数据表(PDF) 291 Page - Freescale Semiconductor, Inc

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