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DSP56303 数据表(PDF) 129 Page - Freescale Semiconductor, Inc |
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DSP56303 数据表(HTML) 129 Page - Freescale Semiconductor, Inc |
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129 / 292 page  Programming Model Quick Reference DSP56303 User’s Manual, Rev. 2 Freescale Semiconductor 6-29 HPCR cont. 4 HREN Host Request Enable 0 1 HDRQ = 0 HDRQ = 1 HREQ/HTRQ = GPIO HREQ/HTRQ HACK/HRRQ = GPIO HREQ/HTRQ = HREQ,HREQ/HTRQ HACK/HRRQ = HTRQ, HRRQ 0— — 5 HAEN Host Acknowledge Enable 0 1 HDRQ = 0 HDRQ=1 HACK/HRRQ = GPIO HREQ/HTRQ HACK/HRRQ = GPIO HACK/HRRQ = HACK HREQ/HTRQ HACK/HRRQ = HTRQ, HRRQ 0— — 6 HEN Host Enable 0 1 Host Port = GPIO Host Port Active 0— — 7 — Reserved 0 Reserved 0 — — 8 HROD Host Request Open Drain 0 1 HREQ/HTRQ/HRRQ = driven HREQ/HTRQ/HRRQ = open drain 0 9 HDSP Host Data Strobe Polarity 0 1 HDS/HRD/HWR active low HDS/HRD/HWR active high 0— — 10 HASP Host Address Strobe Polarity 0 1 HAS active low HAS active high 0— — 11 HMUX Host Multiplexed Bus 0 1 Separate address and data lines Multiplexed address/data 0— — 12 HDDS Host Dual Data Strobe 0 1 Single Data Strobe (HDS) Double Data Strobe (HWR, HRD) 0— — 13 HCSP Host Chip Select Polarity 0 1 HCS active low HCS active high 0— — 14 HRP Host Request Polarity 0 1 HREQ/HTRQ/HRRQ active low HREQ/HTRQ/HRRQ active high 0— — 15 HAP Host Acknowledge Polarity 0 1 HACK active low HACK active high 0— — Table 6-19. HI08 Programming Model, DSP Side (Continued) Register Bit Reset Type Bit No. Bit Name Value Function HW/ SW Indivi- dual STOP |
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