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DSP56303 数据表(PDF) 133 Page - Freescale Semiconductor, Inc |
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DSP56303 数据表(HTML) 133 Page - Freescale Semiconductor, Inc |
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133 / 292 page ![]() DSP56303 User’s Manual, Rev. 2 Freescale Semiconductor 7-1 Enhanced Synchronous Serial Interface (ESSI) 7 The ESSI provides a full-duplex serial port for serial communication with a variety of serial devices, including one or more industry-standard codecs, other DSPs, microprocessors, and peripherals. The ESSI consists of independent transmitter and receiver sections and a common ESSI clock generator. There are two independent and identical ESSIs in the DSP56303: ESSI0 and ESSI1. For simplicity, a single generic ESSI is described here. The ESSI block diagram is shown in Figure 7-1. This interface is synchronous because all serial transfers are synchronized to one clock. This synchronous interface should not be confused with the asynchronous channels mode of the ESSI, in which separate clocks are used for the receiver and transmitter. In that mode, the ESSI is still a synchronous device because all transfers are synchronized to these clocks. Pin notations for the generic ESSI refer to the analogous pin of ESSI0 (PCx) and ESSI1 (PDx). Figure 7-1. ESSI Block Diagram RSMA RSMB TSMA TSMB SSISR RX RX SHIFT REG TX0 SHIFT REG TSR RCLK TX0 CRB CRA SRD STD TCLK SC2 SCK Clock/Frame Sync Generators and Control Logic Interrupts TX1 SHIFT REG TX1 SC0 TX2 SHIFT TX2 SC1 GDB DDB |
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