DSP56303 datasheet(131/292 Pages) FREESCALE

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Programming Model Quick Reference

DSP56303 User’s Manual, Rev. 2

Freescale Semiconductor

6-31

ISR

RXDF

Receive Data Register Full

Host Receive Register is empty

Host Receive Register is full

TXDE

Transmit Data Register

Empty

Host Transmit Register is

empty

Host Transmit Register is full

TRDY

Transmitter Ready

transmit FIFO (6 deep) is

empty

transmit FIFO is not empty

HF2

Host Flag 2

—

HF3

Host Flag 3

—

HREQ

Host Request

HREQ signal is deasserted

HREQ signal is asserted (if

enabled)

CVR

6–0

HV[6–0]

Host Command Vector

$32

—

CVR

Host Command

no host command pending

host command pending

RXH/M/

7–0

Host Receive Data Register

empt

TXH/M/

7–0

Host Transmit Data

empt

IVR

7–0

IV[7–0]

Interrupt Register

68000 family vector register

$0F

—

Table 6-20. HI08 Programming Model: Host Side (Continued)

Reg

Bit

Reset Type

Name

Value

Function

HW/

Indi

vi-d

ual

STOP

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