DSP56303 datasheet(134/292 Pages) FREESCALE

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DSP56303 User’s Manual, Rev. 2

7-2

Freescale Semiconductor

Enhanced Synchronous Serial Interface (ESSI)

Additional synchronization signals delineate the word frames. The Normal mode of operation

transfers data at a periodic rate, one word per period. The Network mode is similar in that it is

also for periodic transfers; however, it supports up to 32 words (time slots) per period. The

Network mode can be used to build time division multiplexed (TDM) networks. In contrast, the

On-Demand mode is for nonperiodic transfers of data. This mode, which offers a subset of the

Freescale Serial Peripheral Interface (SPI) protocol, can transfer data serially at high speed when

the data become available. Since each ESSI unit can be configured with one receiver and three

transmitters, the two units can be used together for surround sound applications (which need two

digital input channels and six digital output channels).

7.1 ESSI Enhancements

The DSP56000 SSI is enhanced in the following ways to make the ESSI:

Network enhancements

— Time slot mask registers (receive and transmit)

— End-of-frame interrupt

— Drive enable signal (used with transmitter 0)

Audio enhancements

— Three transmitters per ESSI (for six-channel surround-sound)

General enhancements

— Can trigger DMA interrupts (receive or transmit)

— Separate exception enable bits

Other changes

— One divide-by-2 step is removed from the internal clock source chain

— The CRA[PSR] bit definition is reversed

— Gated-Clock mode is not available

7.2 ESSI Data and Control Signals

Three to six signals are required for ESSI operation, depending on the operating mode selected.

The serial transmit data (STD) signal and serial control (SC0 and SC1) signals are fully

synchronized to the clock if they are programmed as transmit-data signals.

7.2.1 Serial Transmit Data Signal (STD)

The STD signal transmits data from the serial transmit shift register. STD is an output when data is

transmitted from the TX0 shift register. With an internally-generated bit clock, the STD signal

becomes a high impedance output signal for a full clock period after the last data bit is

transmitted if another data word does not follow immediately. If sequential data words are

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