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DSP56303 数据表(PDF) 135 Page - Freescale Semiconductor, Inc |
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DSP56303 数据表(HTML) 135 Page - Freescale Semiconductor, Inc |
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135 / 292 page  ESSI Data and Control Signals DSP56303 User’s Manual, Rev. 2 Freescale Semiconductor 7-3 transmitted, the STD signal does not assume a high-impedance state. The STD signal can be programmed as a GPIO signal (P5) when the ESSI STD function is not in use. 7.2.2 Serial Receive Data Signal (SRD) SRD receives serial data and transfers the data to the receive shift register. SRD can be programmed as a GPIO signal (P4) when the SRD function is not in use. 7.2.3 Serial Clock (SCK) SCK is a bidirectional signal providing the serial bit rate clock for the ESSI interface. The signal is a clock input or output used by all the enabled transmitters and receivers in Synchronous modes or by all the enabled transmitters in Asynchronous modes. See Table 7-1 for details. SCK can be programmed as a GPIO signal (P3) when not used as the ESSI clock. Note: Although an external serial clock can be independent of and asynchronous to the DSP system clock, the external ESSI clock frequency must not exceed Fcore/3, and each ESSI phase must exceed the minimum of 1.5 CLKOUT cycles. The internally sourced ESSI clock frequency must not exceed Fcore/4. 7.2.4 Serial Control Signal (SC0) ESSI0: SC00; ESSI1: SC10 To determine the function of the SC0 signal, select either Synchronous or Asynchronous mode, according to Table 7-2. In Asynchronous mode, this signal is used for the receive clock I/O. In Synchronous mode, this signal is the transmitter data out signal for transmit shift register TX1 or for serial flag I/O. A typical application of serial flag I/O would be multiple device selection for addressing in codec systems. If SC0 is configured as a serial flag signal or receive clock signal, its direction is determined by the Serial Control Direction 0 (SCD0) bit in ESSI Control Register B (CRB). When configured as an output, SC0 functions as the serial Output Flag 0 (OF0) or as a receive shift register clock Table 7-1. ESSI Clock Sources SYN SCKD SCD0 RX Clock Source RX Clock Out TX Clock Source TX Clock Out Asynchronous 0 0 0 EXT, SC0 — EXT, SCK — 0 0 1 INT SC0 EXT, SCK — 0 1 0 EXT, SC0 — INT SCK 0 1 1 INT SC0 INT SCK Synchronous 1 0 0/1 EXT, SCK — EXT, SCK — 1 1 0/1 INT SCK INT SCK |
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