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DSP56303 数据表(PDF) 136 Page - Freescale Semiconductor, Inc

部件名 DSP56303
功能描述  DSP56303 USER?셎 MANUAL
PDF  292 Pages
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制造商  FREESCALE [Freescale Semiconductor, Inc]
网页  http://www.freescale.com
标志 FREESCALE - Freescale Semiconductor, Inc

DSP56303 数据表(HTML) 136 Page - Freescale Semiconductor, Inc

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DSP56303 User’s Manual, Rev. 2
7-4
Freescale Semiconductor
Enhanced Synchronous Serial Interface (ESSI)
output. If SC0 is used as the serial Output Flag 0, its value is determined by the value of the serial
Output Flag 0 (OF0) bit in the CRB. If SC0 is an input, it functions as either serial Input Flag 0 or
a receive shift register clock input. As serial Input Flag 0, SC0 controls the state of the serial Input
Flag 0 (IF0) bit in the ESSI Status Register (SSISR).
When SC0 is configured as a transmit data signal, it is always an output signal, regardless of the
SCD0 bit value. SC0 is fully synchronized with the other transmit data signals (STD and SC1). SC0
can be programmed as a GPIO signal (P0) when the ESSI SC0 function is not in use.
Note:
The ESSI can operate with more than one active transmitter only in Synchronous
mode.
7.2.5 Serial Control Signal (SC1)
ESSI0:SC01; ESSI1: SCI11
To determine the function of SC1, select either Synchronous or Asynchronous mode, according to
Table 7-2. In Asynchronous mode (as for a single codec with asynchronous transmit and
receive), SC1 is the receiver frame sync I/O. In Synchronous mode, SC1 is the transmitter data out
signal of transmit shift register TX2, for the transmitter 0 drive-enabled signal, or for serial flag
I/O. As serial flag I/O, SC1 operates like SC0. SC0 and SC1are independent flags but can be used
together for multiple serial device selection; they can be unencoded to select up to two CODECs
or decoded externally to select up to four CODECs. If SC1 is configured as a serial flag or receive
frame sync signal, the Serial Control Direction 1 CRB[SCD1] bit determines its direction.
Table 7-2. Mode and Signal Definitions
Control Bits
ESSI Signals
SYN
TE0
TE1
TE2
RE
SC0
SC1
SC2
SCK
STD
SRD
00
X
X
0U
U
U
U
U
U
00
X
X
1
RXC
FSR
U
U
U
RD
01
X
X
0U
U
FST
TXC
TD0
U
0
1
X
X
1
RXC
FSR
FST
TXC
TD0
RD
10
0
0
0U
U
U
U
U
U
1
0
0
0
1
F0/U
F1/T0D/U
FS
XC
U
RD
10
0
1
0
F0/U
TD2
FS
XC
U
U
10
0
1
1
F0/U
TD2
FS
XC
U
RD
1
0
1
0
0
TD1
F1/T0D/U
FS
XC
U
U
1
0
1
0
1
TD1
F1/T0D/U
FS
XC
U
RD
10
1
1
0
TD1
TD2
FS
XC
U
U
1
0
1
1
1
TD1
TD2
FS
XC
U
RD
1
1
0
0
0
F0/U
F1/T0D/U
FS
XC
TD0
U



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