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ADE9178 数据表(PDF) 101 Page - Analog Devices |
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ADE9178 数据表(HTML) 101 Page - Analog Devices |
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101 / 122 page  Data Sheet ADE9178 REGISTER DETAILS: ADE9178 analog.com Rev. A | 101 of 122 Table 34. ADE9178 Register Details (Continued) Addr Name Bits Bit Name Settings Description Reset Access dip condition and is zero when it is not in a dip condition, as calculated by RMSONE. 4 CVDIPONE Phase C Voltage Dip Condition Detected. This bit is set when the phase C voltage is in the dip condition and is zero when it is not in a dip condition, as calculated by RMSONE. 0x0 R/W1C 3 BIDIPONE Phase B Current Dip Condition Detected. This bit is set when the phase B current is in the dip condition and is zero when it is not in a dip condition, as calculated by RMSONE. 0x0 R/W1C 2 BVDIPONE Phase B Voltage Dip Condition Detected. This bit is set when the phase B voltage is in the dip condition and is zero when it is not in a dip condition, as calculated by RMSONE. 0x0 R/W1C 1 AIDIPONE Phase A Current Dip Condition Detected. This bit is set when the phase A current is in the dip condition and is zero when it is not in a dip condition, as calculated by RMSONE. 0x0 R/W1C 0 AVDIPONE Phase A Voltage Dip Condition Detected. This bit is set when the phase A voltage is in the dip condition and is zero when it is not in a dip condition, as calculated by RMSONE. 0x0 R/W1C 0x403 STATUS3 [31:24] RESERVED Reserved. 0x0 R 23 AUX5SWELLHALF Auxiliary 5 Channel Swell Condition Detected. This bit is set when the AUX5 channel is in the swell condition and is zero when it is not in a swell condition, as calculated by RMSHALF. 0x0 R/W1C 22 AUX4SWELLHALF Auxiliary 4 Channel Swell Condition Detected. This bit is set when the AUX4 channel is in the swell condition and is zero when it is not in a swell condition, as calculated by RMSHALF. 0x0 R/W1C 21 AUX3SWELLHALF Auxiliary 3 Channel Swell Condition Detected. This bit is set when the AUX3 channel is in the swell condition and is zero when it is not in a swell condition, as calculated by RMSHALF. 0x0 R/W1C |
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