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ADE9178 数据表(PDF) 103 Page - Analog Devices

部件名 ADE9178
功能描述  Energy Management DSP with PEN Fault Detection
PDF  122 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADE9178 数据表(HTML) 103 Page - Analog Devices

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Data Sheet
ADE9178
REGISTER DETAILS: ADE9178
analog.com
Rev. A | 103 of 122
Table 34. ADE9178 Register Details (Continued)
Addr
Name
Bits
Bit Name
Settings
Description
Reset
Access
12
AVSWELLHALF
Phase A Voltage Swell
Condition Detected. This bit is
set when the phase A voltage
is in the swell condition and
is zero when it is not in a
swell condition, as calculated
by RMSHALF.
0x0
R/W1C
11
AUX5DIPHALF
Auxiliary 5 Channel Dip
Condition Detected. This bit is
set when the AUX5 channel is
in the dip condition and is zero
when it is not in a dip condition,
as calculated by RMSHALF.
0x0
R/W1C
10
AUX4DIPHALF
Auxiliary 4 Channel Dip
Condition Detected. This bit is
set when the AUX4 channel is
in the dip condition and is zero
when it is not in a dip condition,
as calculated by RMSHALF.
0x0
R/W1C
9
AUX3DIPHALF
Auxiliary 3 Channel Dip
Condition Detected. This bit is
set when the AUX3 channel is
in the dip condition and is zero
when it is not in a dip condition,
as calculated by RMSHALF.
0x0
R/W1C
8
AUX2DIPHALF
Auxiliary 2 Channel Dip
Condition Detected. This bit is
set when the AUX2 channel is
in the dip condition and is zero
when it is not in a dip condition,
as calculated by RMSHALF.
0x0
R/W1C
7
AUX1DIPHALF
Auxiliary 1 Channel Dip
Condition Detected. This bit is
set when the AUX1 channel is
in the dip condition and is zero
when it is not in a dip condition,
as calculated by RMSHALF.
0x0
R/W1C
6
AUX0DIPHALF
Auxiliary 0 Channel Dip
Condition Detected. This bit is
set when the AUX0 channel is
in the dip condition and is zero
when it is not in a dip condition,
as calculated by RMSHALF.
0x0
R/W1C
5
CIDIPHALF
Phase C Current Dip Condition
Detected. This bit is set when
the phase C current is in the
dip condition and is zero when
it is not in a dip condition, as
calculated by RMSHALF.
0x0
R/W1C
4
CVDIPHALF
Phase C Voltage Dip Condition
Detected. This bit is set when
the phase C voltage is in the
dip condition and is zero when
it is not in a dip condition, as
calculated by RMSHALF.
0x0
R/W1C



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