ADE9178 datasheet(105/122 Pages) AD

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Data Sheet

ADE9178

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Rev. A | 105 of 122

Table 34. ADE9178 Register Details (Continued)

Addr

Name

Bits

Bit Name

Settings

Description

Reset

Access

ADC1_STATUS2

ADC1 STATUS2. This bit is

set when one or more bits of

STATUS2 register of ADC1 are

set.

0x0

R/W1C

ADC1_STATUS1

ADC1 STATUS1. This bit is

set when one or more bits of

STATUS1 register of ADC1 are

set.

0x0

R/W1C

ADC1_STATUS0

ADC1 STATUS0. This bit is

set when one or more bits of

STATUS0 register of ADC1 are

set.

0x0

R/W1C

ADC0_STATUS2

ADC0 STATUS2. This bit is

set when one or more bits of

STATUS2 register of ADC0 are

set.

0x0

R/W1C

ADC0_STATUS1

ADC0 STATUS1. This bit is

set when one or more bits of

STATUS1 register of ADC0 are

set.

0x0

R/W1C

ADC0_STATUS0

ADC0 STATUS0. This bit is

set when one or more bits of

STATUS0 register of ADC0 are

set.

0x0

R/W1C

DREADY_FREQ_ERROR

ADC Data Ready Frequency

Error. This bit is set when ADC

Data Ready frequency is not

4 kHz. If the bit is set then

new input samples will not be

processed and output registers

will not be updated.

0x0

R/W1C

ERROR5

Internal Error. Reset ADE9178

and ADCs.

0x0

R/W1C

ADC_CRC_ERROR

ADC CRC Error Occurs. This

bit is set when ADC CRC error

occurs.

0x0

R/W1C

ERROR4

Internal Error. Reset ADE9178

and ADCs.

0x0

R/W1C

ERROR3

Internal Error. Reset ADE9178

and ADCs.

0x0

R/W1C

ERROR2

Internal Error. Reset ADE9178

and ADCs.

0x0

R/W1C

ERROR1

Internal Error. Reset ADE9178

and ADCs.

0x0

R/W1C

ERROR0

Internal Error. Reset ADE9178

and ADCs.

0x0

R/W1C

ADC_INIT_ERROR

Error Occurs in ADC

Initialization. This bit is set

when error occurs in ADC

initialization.

0x0

R/W1C

0x405

MASK0

ZXAUX5

Auxiliary 5 Channel Zero

Crossing Detected Mask. Set

this bit to enable an interrupt

0x0

R/W

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