ADE9178 datasheet(111/122 Pages) AD

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Data Sheet

ADE9178

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Rev. A | 111 of 122

Table 34. ADE9178 Register Details (Continued)

Addr

Name

Bits

Bit Name

Settings

Description

Reset

Access

by the configuration register

CRC change value. The

CRC_RSLT register holds the

new configuration register CRC

value.

VANLOAD

Total Apparent Energy No Load

Condition Changed Mask. Set

this bit to enable an interrupt

when one or more phase of

total apparent energy enters or

exits the no load condition.

0x0

R/W

WATTNLOAD

Total Active Energy No Load

Condition Changed Mask. Set

this bit to enable an interrupt

when one or more phase of

total active energy enters or

exits the no load condition.

0x0

R/W

ISUMMISMTCH

ISUM RMS Mismatch Mask.

Set this bit to enable an

interrupt when there is a

change in the relationship

between ISUMRMS and

ISUMLVL.

0x0

R/W

PF_RDY

Power Factor Data Ready

Mask. Set this bit to enable an

interrupt when the power factor

measurements update, every 1

sec.

0x0

R/W

RMSONERDY

One-Cycle RMS Data Ready

Mask. Set this bit to enable an

interrupt when the one cycle

RMS values are updated.

0x0

R/W

CF2

CF2 Pulse Issued Mask. Set

this bit to enable an interrupt

when a CF2 pulse is issued,

when the CF2 pin goes from a

high to low state.

0x0

R/W

CF1

CF1 Pulse Issued Mask. Set

this bit to enable an interrupt

when a CF1 pulse is issued,

when the CF1 pin goes from a

high to low state.

0x0

R/W

REVPSUM2

CF2 Polarity Sign Change

Mask. Set this bit to enable an

interrupt when the CF2 polarity

changed sign.

0x0

R/W

REVPSUM1

CF1 Polarity Sign Change

Mask. Set this bit to enable an

interrupt when the CF1 polarity

changed sign.

0x0

R/W

REVAPC

Phase C Active Power Sign

Change Mask. Set this bit to

enable an interrupt when the

phase C active power has

changed sign.

0x0

R/W

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