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ADE9178 数据表(PDF) 113 Page - Analog Devices |
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ADE9178 数据表(HTML) 113 Page - Analog Devices |
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113 / 122 page  Data Sheet ADE9178 REGISTER DETAILS: ADE9178 analog.com Rev. A | 113 of 122 Table 34. ADE9178 Register Details (Continued) Addr Name Bits Bit Name Settings Description Reset Access 25 VABDIPONE VP2P Dip Condition Detected. Set this bit to enable an interrupt when the VP2P (AV − BV) voltage is in the dip condition and is zero when it is not in a dip condition, as calculated by RMSONE. 0x0 R/W 24 VSUMSWELLONE VSUM Swell Condition Detected. Set this bit to enable an interrupt when the sum of voltage channels is in the swell condition and is zero when it is not in a swell condition, as calculated by RMSONE. 0x0 R/W 23 AUX5SWELLONE Auxiliary 5 Channel Swell Condition Detected. Set this bit to enable an interrupt when the AUX5 channel is in the swell condition and is zero when it is not in a swell condition, as calculated by RMSONE. 0x0 R/W 22 AUX4SWELLONE Auxiliary 4 Channel Swell Condition Detected. Set this bit to enable an interrupt when the AUX4 channel is in the swell condition and is zero when it is not in a swell condition, as calculated by RMSONE. 0x0 R/W 21 AUX3SWELLONE Auxiliary 3 Channel Swell Condition Detected. Set this bit to enable an interrupt when the AUX3 channel is in the swell condition and is zero when it is not in a swell condition, as calculated by RMSONE. 0x0 R/W 20 AUX2SWELLONE Auxiliary 2 Channel Swell Condition Detected. Set this bit to enable an interrupt when the AUX2 channel is in the swell condition and is zero when it is not in a swell condition, as calculated by RMSONE. 0x0 R/W 19 AUX1SWELLONE Auxiliary 1 Channel Swell Condition Detected. Set this bit to enable an interrupt when the AUX1 channel is in the swell condition and is zero when it is not in a swell condition, as calculated by RMSONE. 0x0 R/W 18 AUX0SWELLONE Auxiliary 0 Channel Swell Condition Detected. Set this bit to enable an interrupt when the AUX0 channel is in the swell condition and is zero when it is not in a swell condition, as calculated by RMSONE. 0x0 R/W |
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