H8SSLASH2214 datasheet(274/936 Pages) RENESAS

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Section 7 DMA Controller

Rev.4.00 Sep. 18, 2008 Page 214 of 872

REJ09B0189-0400

7.5.3

Idle Mode

Idle mode can be specified by setting the RPE bit and DTIE bit in DMACR to 1. In idle mode, one

byte or word is transferred in response to a single transfer request, and this is executed the number

of times specified in ETCR.

One address is specified by MAR, and the other by IOAR. The transfer direction can be specified

by the DTDIR bit in DMACR.

Table 7.8 summarizes register functions in idle mode.

Table 7.8

Function

DTDIR = 0 DTDIR = 1 Initial Setting

Operation

MAR

Source

address

Destination

address

Start address of

transfer destination

or transfer source

Fixed

IOAR

H'FF

Destination

address

Source

address

Start address of

transfer source or

transfer destination

Fixed

ETCR

Transfer counter

Number of transfers Decremented every

transfer; transfer

ends when count

reaches H'0000

Legend:

MAR:

Memory address register

IOAR:

I/O address register

ETCR:

Transfer count register

DTDIR: Data transfer direction bit

MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is

neither incremented nor decremented each time a byte or word is transferred.

IOAR specifies the lower 16 bits of the other address. The 8 bits above IOAR have a value of

H'FF.

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