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AM79C971VCW 数据表(PDF) 106 Page - Advanced Micro Devices |
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AM79C971VCW 数据表(HTML) 106 Page - Advanced Micro Devices |
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106 / 265 page  106 Am79C971 Table 24. I/O Map In DWord I/O Mode (DWIO = 1) Table 25. Legal I/O Accesses in Double Word I/O Mode (DWIO =1) USER ACCESSIBLE REGISTERS The Am79C971 controller has three types of user reg- isters: the PCI configuration registers, the Control and Status registers (CSR), and the Bus Control registers (BCR). The Am79C971 controller implements all PCnet-ISA (Am79C960) registers, all C-LANCE (Am79C90) regis- ters, plus a number of additional registers. The Am79C971 controller CSRs are compatible upon power up with both the PCnet-ISA CSRs and all of the C-LANCE CSRs. The PCI configuration registers can be accessed in any data width. All other registers must be accessed ac- cording to the I/O mode that is currently selected. When WIO mode is selected, all other register loca- tions are defined to be 16 bits in width. When DWIO mode is selected, all these register locations are de- fined to be 32 bits in width, with the upper 16 bits of most register locations marked as reserved locations with undefined values. When performing register write operations in DWIO mode, the upper 16 bits should al- ways be written as zeros. When performing register read operations in DWIO mode, the upper 16 bits of I/ O resources should always be regarded as having un- defined values, except for CSR88. The Am79C971 registers can be divided into four groups: PCI Configuration, Setup, Running, and Test. Registers not included in any of these categories can be assumed to be intended for diagnostic purposes. Table 23. Legal I/O Accesses in Word I/O Mode (DWIO = 0) AD[4:0] BE[3:0] Type Comment 0XX00 1110 RD Byte read of APROM location 0h, 4h, 8h or Ch 0XX01 1101 RD Byte read of APROM location 1h, 5h, 9h or Dh 0XX10 1011 RD Byte read of APROM location 2h, 6h, Ah or Eh 0XX11 0111 RD Byte read of APROM location 3h, 7h, Bh or Fh 0XX00 1100 RD Word read of APROM locations 1h (MSB) and 0h (LSB), 5h and 4h, 8h and 9h or Ch and Dh 0XX10 0011 RD Word read of APROM locations 3h (MSB) and 2h (LSB), 7h and 6h, Bh and Ah or Fh and Eh 10000 1100 RD Word read of RDP 10010 0011 RD Word read of RAP 10100 1100 RD Word read of Reset Register 10110 0011 RD Word read of BDP 0XX00 1100 WR Word write to APROM locations 1h (MSB) and 0h (LSB), 5h and 4h, 8h and 9h or Ch and Dh 0XX10 0011 WR Word write to APROM locations 3h (MSB) and 2h (LSB), 7h and 6h, Bh and Ah or Fh and Eh 10000 1100 WR Word write to RDP 10010 0011 WR Word write to RAP 10100 1100 WR Word write to Reset Register 10110 0011 WR Word write to BDP 10000 0000 WR DWord write to RDP, switches device to DWord I/O mode Offset No. of Bytes Register 00h - 0Fh 16 APROM 10h 4 RDP 14h 4 RAP (shared by RDP and BDP) 18h 4 Reset Register 1Ch 4 BDP AD[4:0] BE[3:0] Type Comment 0XX00 0000 RD DWord read of APROM locations 3h (MSB) to 0h (LSB), 7h to 4h, Bh to 8h or Fh to Ch 10000 0000 RD DWord read of RDP 10100 0000 RD DWord read of RAP 11000 0000 RD DWord read of Reset Register 11100 0000 RD DWord read of BDP 0XX00 0000 WR DWord write to APROM locations 3h (MSB) to 0h (LSB), 7h to 4h, Bh to 8h or Fh to Ch 10000 0000 WR DWord write to RDP 10100 0000 WR DWord write to RAP 11000 0000 WR DWord write to Reset Register 11100 0000 WR DWord write of BDP |
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