EM357-RTR datasheet(179/241 Pages) SILABS

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179

Rev 1.3

10.5. ADC Key Parameters

Table 10.6 describes the key ADC parameters measured on Silicon Labs’ EM357 reference design at 25 °C and

VDD_PADS at 3.0 V, for a sampling clock of 1 MHz. The single-ended measurements were done at finput = 7.7%

fNyquist; 0 dBFS level (where full-scale is a 1.2 V p-p swing). The differential measurements were done at

finput = 7.7% fNyquist; –6 dBFS level (where full-scale is a 2.4 V p-p swing) and a common mode voltage of 0.6 V.

Table 10.6. ADC Module Key Parameters for 1 MHz Sampling

Parameter

Performance

ADC_PERIOD

Conversion Time (µs)

128

256

512

1024

2048

4096

Nyquist Freq (kHz)

15.6k

7.81k

3.91k

1.95k

977

488

244

122

3 dB Cut-off (kHz)

9.43k

4.71k

2.36k

1.18k

589

295

147

73.7

INL (codes peak)1

0.083

0.092

0.163

0.306

0.624

1.229

2.451

4.926

INL (codes RMS)1

0.047

0.051

0.093

0.176

0.362

0.719

1.435

2.848

DNL (codes peak)1

0.028

0.035

0.038

0.044

0.074

0.113

0.184

0.333

DNL (codes RMS)1

0.008

0.009

0.011

0.014

0.019

0.029

0.048

0.079

ENOB

(from single-cycle test)

5.6

7.0

8.6

10.1

11.5

12.6

13.0

13.2

SNR (dB)2

Single-Ended

Differential

SINAD (dB)2

Single-Ended

Differential

SDFR (dB)

Single-Ended

Differential

THD (dB)

Single-Ended

Differential

–45

–54

–62

–63

–67

–71

–69

–75

–69

–76

–69

–76

–69

–76

ENOB (from SNR)2

Single-Ended

Differential

5.6

7.1

8.6

10.0

10.1

11.3

11.4

12.2

12.5

12.4

12.9

12.5

12.9

ENOB (from SINAD)2

Single-Ended

Differential

5.5

5.6

7.0

8.5

9.9

10.0

10.9

11.3

11.2

12.1

11.3

12.3

11.3

12.4

Equivalent ADC Bits1

[15:9]

[15:8]

[15:7]

[15:6]

[15:5]

[15:4]

[15:3]

[15:2]

Notes:

INL and DNL are referenced to a LSB of the Equivalent ADC Bits shown in the last row of this table.

ENOB (effective number of bits) can be calculated from either SNR (signal to non-harmonic noise ratio) or SINAD

(signal-to-noise and distortion ratio).

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