TNETV2664FIBZWT datasheet(16/249 Pages) TI1

16 / 249 page

TMS320C6424

SPRS347D – MARCH 2007 – REVISED DECEMBER 2009

www.ti.com

The L1P is divided into two regions—denoted as L1P Region 0 and L1P Region 1. This is the L1P

architecture on the C6424:

•

L1P Region 0: 0K-Byte Memory

•

L1P Region 1: 32K-Byte Memory

–

L1P Region 1 can be configured as mapped memory or cache and has a 0 wait state latency. This

region is shown as "L1P RAM/Cache" in Table 2-5, Memory Map Summary.

The C6424 does not support memory protection on L1P.

The L1D is divided into two regions—denoted as L1D Region 0 and L1D Region 1. This is the L1D

architecture on the C6424:

•

L1D Region 0: 48K-Byte Memory

–

This region is shown as "L1D RAM" in Table 2-5, Memory Map Summary.

•

L1D Region 1: 32K-Byte Memory

–

L1D Region 1 can be configured as mapped memory or cache. This region is shown as "L1D

RAM/Cache" in Table 2-5, Memory Map Summary.

The C6424 does not support memory protection on L1D.

L2 memory implements two separate memory ports. This is the L2 architecture on the C6424:

•

Port 0

–

This port is shown as "L2 RAM/Cache" in Table 2-5, Memory Map Summary.

–

Banking Scheme: 2 x 128-bit banks

–

Latency: 1 cycle (0 wait state)

•

Port 1

–

This port is shown as "Boot ROM" in Table 2-5, Memory Map Summary.

–

Banking Scheme: 1 x 256-bit bank

–

Latency: 1 cycle (0 wait state)

The C6424 does not support memory protection on L2.

For more detailed information about the C64x+ Cache Memory Architecture, see the TMS320C64x+ DSP

Cache User's Guide (literature number SPRU862) and the TMS320C64x+ DSP Megamodule Reference

Guide (literature number SPRU871).

2.2.2.1

L1P Configuration Register (L1PCFG) Description

The L1P Configuration Register (L1PCFG) controls/defines the size of the L1P cache. On the C6424, the

L1PCFG register is device-specific and varies from what is shown in the TMS320C64x+ DSP

Megamodule Reference Guide (literature number SPRU871). The format and bit field descriptions of the

L1PCFG register for the C6424 are shown in Figure 2-4 and Table 2-3, respectively.

Device Overview

Submit Documentation Feedback

Product Folder Link(s): TMS320C6424

TNETV2664FIBZWT 数据表(PDF) 16 Page - Texas Instruments

TNETV2664FIBZWT 数据表(HTML) 16 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载