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TNETV2664FIBZWT 数据表(PDF) 97 Page - Texas Instruments |
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TNETV2664FIBZWT 数据表(HTML) 97 Page - Texas Instruments |
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97 / 249 page  TMS320C6424 www.ti.com SPRS347D – MARCH 2007 – REVISED DECEMBER 2009 Table 3-19. Multiplexed Pins on C6424 (continued) SIGNAL PINMUX DESCRIPTION ZWT ZDU NAME PINMUX GROUP CONTROLLED BY PINMUX BIT FIELDS NO. NO. RMRXD0/EM_CS4/GP[32] E19 H22 EMIFA Sub-Block 1 RMII, CS4SEL REFCLK/GP[31] D19 G22 EMIFA Sub-Block 1 RMII RMCRSDV/GP[30] G19 K22 EMIFA Sub-Block 1 RMII RMTXEN/GP[29] H15 K21 EMIFA Sub-Block 1 RMII RMTXD0/GP[28] H16 J21 EMIFA Sub-Block 1 RMII RMTXD1/GP[27] H17 L19 EMIFA Sub-Block 1 RMII GP[26]/(FASTBOOT) G17 K19 EMIFA Sub-Block 1 - GP[25]/(BOOTMODE3) G16 H21 EMIFA Sub-Block 1 - GP[24]/(BOOTMODE2) G15 L20 EMIFA Sub-Block 1 - GP[23]/(BOOTMODE1) F15 K20 EMIFA Sub-Block 1 - GP[22]/(BOOTMODE0) F18 J20 EMIFA Sub-Block 1 - EM_D[7]/GP[21] F17 H20 EMIFA Sub-Block 1 AEM EM_D[6]/GP[20] F16 F21 EMIFA Sub-Block 1 AEM EM_D[5]/GP[19] E17 F22 EMIFA Sub-Block 1 AEM EM_D[4]/GP[18] E18 G21 EMIFA Sub-Block 1 AEM EM_D[3]/GP[17] E16 F20 EMIFA Sub-Block 1 AEM EM_D[2]/GP[16] D17 E22 EMIFA Sub-Block 1 AEM EM_D[1]/GP[15] D18 G20 EMIFA Sub-Block 1 AEM EM_D[0]/GP[14] D16 E21 EMIFA Sub-Block 1 AEM EM_ CS3/GP[13] C18 D22 EMIFA Sub-Block 1 CS3SEL EM_CS2/GP[12] C19 C22 EMIFA Sub-Block 1 AEM EM_A[3]/GP[11] B18 D21 EMIFA Sub-Block 1 AEM EM_A[4]/GP[10]/(PLLMS2) A17 B21 EMIFA Sub-Block 1 AEM EM_A[1]/(ALE)/GP[9]/(PLLMS1) A16 B20 EMIFA Sub-Block 1 AEM EM_A[2]/(CLE)/GP[8]/(PLLMS0) B16 A20 EMIFA Sub-Block 1 AEM EM_A[0]/GP[7]/(AEM2) B17 C21 EMIFA Sub-Block 1 AEM EM_BA[0]/GP[6]/(AEM1) C17 E20 EMIFA Sub-Block 1 AEM EM_BA[1]/GP[5]/(AEM0) C16 C20 EMIFA Sub-Block 1 AEM EM_A[12]/PCBE3/GP[89] D10 B12 EMIFA Sub-Block 3 PCIEN, AEM EM_A[11]/AD24/GP[90] C10 C12 EMIFA Sub-Block 3 PCIEN, AEM EM_A[10]/AD23/GP[91] A9 B11 EMIFA Sub-Block 3 PCIEN, AEM EM_A[9]/PIDSEL/GP[92] D9 C11 EMIFA Sub-Block 3 PCIEN, AEM EM_A[8]/AD21/GP[93] B9 A11 EMIFA Sub-Block 3 PCIEN, AEM EM_A[7]/AD22/GP[94] C9 C10 EMIFA Sub-Block 3 PCIEN, AEM EM_A[6]/AD20/GP[95] D8 B10 EMIFA Sub-Block 3 PCIEN, AEM EM_A[5]/AD19/GP[96] B8 A10 EMIFA Sub-Block 3 PCIEN, AEM VLYNQ_CLOCK/PCICLK/GP[57] A7 A8 Host Block PCIEN, HOSTBK HD0/VLYNQ_SCRUN/AD18/GP[58] C8 B9 Host Block PCIEN, HOSTBK HD1/VLYNQ_RXD0/AD16/GP[59] D7 C9 Host Block PCIEN, HOSTBK HD2/VLYNQ_RXD1/AD17/GP[60] A8 A9 Host Block PCIEN, HOSTBK HD3/VLYNQ_RXD2/PCBE2/GP[61] B7 B8 Host Block PCIEN, HOSTBK HD4/VLYNQ_RXD3/PFRAME/GP[62] C7 C8 Host Block PCIEN, HOSTBK HD5/VLYNQ_TXD0/PIRDY/GP[63] A6 A7 Host Block PCIEN, HOSTBK HD6/VLYNQ_TXD1/PTRDY/GP[64] D6 C7 Host Block PCIEN, HOSTBK HD7/VLYNQ_TXD2/PDEVSEL/GP[65] B6 B7 Host Block PCIEN, HOSTBK HD8/VLYNQ_TXD3/PPERR/GP[66] A5 A6 Host Block PCIEN, HOSTBK HD9/MCOL/PSTOP/GP[67] C6 C6 Host Block PCIEN, HOSTBK HD10/MCRS/PSERR/GP[68] B5 B6 Host Block PCIEN, HOSTBK HD11/MTXD3/PCBE1/GP[69] C5 A5 Host Block PCIEN, HOSTBK Copyright © 2007–2009, Texas Instruments Incorporated Device Configurations 97 Submit Documentation Feedback Product Folder Link(s): TMS320C6424 |
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