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TNETV2664FIBZWT 数据表(PDF) 89 Page - Texas Instruments |
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TNETV2664FIBZWT 数据表(HTML) 89 Page - Texas Instruments |
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89 / 249 page  TMS320C6424 www.ti.com SPRS347D – MARCH 2007 – REVISED DECEMBER 2009 3.7.1 Pin Muxing Selection At Reset This section summarizes pin mux selection at reset. The configuration pins AEM[2:0] and PCIEN latched at device reset determine default pin muxing for the following Pin Mux Blocks: • EMIFA Block: default pin mux determined by AEM[2:0], RMII, and PCIEN. After reset, software may modify settings in the PINMUX0 register to fine tune pin muxing in this block. However, after reset, software is not allowed to modify PINMUX1.PCIEN setting to change PCI pinout. – PCIEN = 0, AEM[2:0] = 000b, RMII = 0: Major Config Option A is selected. This block defaults to 58 GPIO pins. – PCIEN = 0, AEM[2:0] = 010b, RMII = 0: Major Config Option C is selected. This block defaults to 16-bit EMIFA (Async) Pinout Mode 2, plus 13 to 16 GPIO pins. – PCIEN = 0, AEM[2:0] = 101b, RMII = 0: Major Config Option E is selected. This block defaults to 8-bit EMIFA (NAND) Pinout Mode 5, plus 44 to 47 GPIO pins. – PCIEN = 1, AEM[2:0] = 000b, RMII = 0: Major Config Option G is selected. This block defaults to PCI and 42 GPIO pins. – PCIEN = 1, AEM[2:0] = 101b, RMII = 0: Major Config Option J is selected. This block defaults to PCI, 8-bit EMIFA (NAND) Pinout Mode 5, and 28 to 31 GPIO pins. • Host Block: default pin mux determined by PCIEN. – PCIEN = 0: the 27 pins in Host Block default to GPIO function. Software may program PINMUX1.HOSTBK to modify pin functions after reset. – PCIEN = 1: the 27 pins in Host Block serve as PCI pins. Software is not allowed to modify this setting after reset. • GPIO Block: pin function determined by PCIEN configuration pin. – PCIEN = 0: the 4 pins in GPIO Block serve as GPIO pins. Software is not allowed to modify this setting after reset. – PCIEN = 1: the 4 pins in GPIO Block serve as PCI pins. Software is not allowed to modify this setting after reset. • PCI Data Block: pin function determined by PCIEN. – PCIEN = 0: the 3 pins in PCI Data Block have no function and should be left unconnected. Software is not allowed to modify this setting after reset. – PCIEN = 1: the 3 pins in PCI Data Block serve as PCI pins. Software is not allowed to modify this setting after reset. For a description of the PINMUX0 and PINMUX1 registers and more details on pin muxing, see Section 3.7.2. 3.7.2 Pin Muxing Selection After Reset The PINMUX0 and PINMUX1 registers in the System Module allow software to select the pin functions in the Pin Mux Blocks. The pin control of some of the Pin Mux Blocks requires a combination of PINMUX0/PINMUX1 bit fields. For more details on the combination of the PINMUX bit fields that control each muxed pin, see Section 3.7.3.1, Multiplexed Pins on C6424. This section only provides an overview of the PINMUX0 and PINMUX1 registers. For more detailed discussion on how to program each Pin Mux Block, see Section 3.7.3, Pin Multiplexing Details. 3.7.2.1 PINMUX0 Register Description The Pin Multiplexing 0 Register (PINMUX0) controls the pin function in the EMIFA Block. The PINMUX0 Copyright © 2007–2009, Texas Instruments Incorporated Device Configurations 89 Submit Documentation Feedback Product Folder Link(s): TMS320C6424 |
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